Intel: The Tigerton roars!

[BaronMatrix]

The Register has a blurb about Intel demoing the Quad Core Tigerton today. It is expected to appear in select systems by the start of November.

Linkage

They still don't expect 4P until next year though.

 

[ElMoIsEviL]

The Register has a blurb about Intel demoing the Quad Core Tigerton today. It is expected to appear in select systems by the start of November.

Linkage

They still don't expect 4P until next year though.

Not sure about the release dates... but..

Tigerton is the product that will complete the Xeon range's shift to multicore. In a briefing in San Francisco last week, the vendor powered up a server running four Tigertons, meaning the beast was running 16 cores in total. The system was running the Clarksboro chipset, which means individual links between each chip and the chipset, and ends those worries about bottlenecks.

Here's some Info regarding Clarksboro CLICK ME!!

The latest chip is also paired with a new MCH. The Clarksboro, which supports FB-DIMM technology (Fully buffered) and introduces support for the new Bus architecture, CSI (Common System Interface). Best used for their processor Independent Bus connection to the MCH.

As I had stated and argued over CSI will make it into Clarksboro, in other words Tigerton.

 

[theaxemaster]

So similar launch windows, that will be an interesting few months. I'm disappointed that the K8L won't be bringing HT3.0 with it while the Tigerton will be using CSI. I'm anxious to see what kind of performance difference that makes for intel.

 

[ElMoIsEviL]

So similar launch windows, that will be an interesting few months. I'm disappointed that the K8L won't be bringing HT3.0 with it while the Tigerton will be using CSI. I'm anxious to see what kind of performance difference that makes for intel.

One can logically assume that it won't have an impact on Tigerton when it is in Single socket form (meaning a single Dual Core or Quad Core Tigerton will not benefit). But it should make a difference once you start pilling up the Sockets as each core will have it's own dedicated Link. I say this because we know that Core 2 Quad does not benefit from a larger Front Side Bus as examined by THG. Therefore it is only logical that the same would apply for a single Quad Core Tigerton.

The Link is also Serial instead of the current parallel FSB. This should reduce the footprint on the motherboard thus decreasing costs and reducing layers needed as well as affecting power consumption in a positive manner.

Of course this is all logical assumptions.

 

[dasickninja]

Hmmmm..... [reads thread title]
This needs an appropriate image:

 

[Parrot]

I'm disappointed that the K8L won't be bringing HT3.0 with it while the Tigerton will be using CSI.

K8L WILL have HT3.0!!!

 

[gOJDO]

So similar launch windows, that will be an interesting few months. I'm disappointed that the K8L won't be bringing HT3.0 with it while the Tigerton will be using CSI. I'm anxious to see what kind of performance difference that makes for intel.

K8L will have HTT3, but the DDR3 ODMC will be postponed for the 45nm shrink.
With the CSI, Intel CPUs will scalle more linear in the MP platform. CSI will help Intel to compete in the 4P+ server area, where AMD have no competition right now. HTT3 will enable more CPUs(8 total) to be directly connected to each other and the performance will scale more linear than current 8P solutions.
Both CSI & HTT3 are good solutions and the performance of the MP systems will be dependend on the CPUs performance.


Here is some more info, about the subject:
http://www.internetnews.com/bus-news/article.php/3639366

 

[quantumsheep]

I'm disappointed that the K8L won't be bringing HT3.0 with it while the Tigerton will be using CSI.

K8L WILL have HT3.0!!!

I was pretty sure K8L would be released with HT 2.0, as the AM2+ will be the only valid socket for it, and AM2+ only supports HT 2.0. I could be mistaken, and probably am. I'll go away and find some links..

 

[Parrot]

I'm disappointed that the K8L won't be bringing HT3.0 with it while the Tigerton will be using CSI.

K8L WILL have HT3.0!!!

I was pretty sure K8L would be released with HT 2.0, as the AM2+ will be the only valid socket for it, and AM2+ only supports HT 2.0. I could be mistaken, and probably am. I'll go away and find some links..
Socket AM2+ supports HT3. HT3 is backwards compatible with HT2. The K8L IMC supports both DDR2 AND DDR3!

 

[theaxemaster]

I'm disappointed that the K8L won't be bringing HT3.0 with it while the Tigerton will be using CSI.

K8L WILL have HT3.0!!!

Not in the first iterration, that's what I was talking about. Eventually, sure, but not until well into 2008.

AMD is going to have to get moving if they want to hold off intel in the server arena.

 

[gOJDO]

Socket AM2+ supports HT3. HT3 is backwards compatible with HT2. The K8L IMC supports both DDR2 AND DDR3!

The 65nm K8L which will come Q3 2007 will have DDR2 ODMC and will be sAM2 and sAM2+ compatible. The 45nm shrink of K8L will have DDR3 and DDR2 ODMC and will be sAM3 compatible.

Pay attention on the picture, "DDR2 with migration path to DDR3"

http://www.hkepc.com/bbs/itnews.php?tid=678954

According to the previous plan, K8L processors as well as the new Quad Core are both based on Socket AM3 with build-in DDR2/3 memory controller, and are compatible with the existing AM2 main board. Yet AMD has decided to postpone AM3 as they reviewed the market trend of DDR3 memory.

According to the latest roadmap for memory module from Samsung, DDR3 is ready right now, where samples of DDR3-800/1066/1333 have been sent to related partners. DDR3 is expected to be available in Q2 2007 with 70nm manufacturing process, and soon to replace DDR2 in mid-2008. It’s clever to put down the non-common DDR3 support into the processors as it complicated the design as well as increased the cost. Releasing the DDR3 supported AM3 till mid-2008 is somewhat reasonable.

http://www.digitimes.com/NewsShow/Article_print.asp?datePublish=2006/10/03&pages=A2&seq=4

Advanced Micro Devices (AMD) has postponed launch of its Socket AM3 processors to the middle of 2008, from an originally scheduled third-quarter 2007, according to motherboard makers. AMD's first quad-core K8L desktop processor, the Altair, originally set to utilize the Socket AM3 connector, will be resident in Socket AM2+, indicated the makers.

The difference between AMD's Socket AM2 and Socket AM2+ is that the former adopts HyperTransport 1.0 and the latter HyperTransport 3.0, the makers indicated. Socket AM2+ is considered a transitional solution for AMD's K8L CPUs, the makers added.

Socket AM3 CPUs can only be compatible with Socket AM2- and Socket AM3-based motherboards, but Socket AM3-based motherboards cannot support any previous-generation processors, including Socket AM2 CPUs, the makers noted. Consequently, AMD has decided to postpone the adoption of DDR3 until the middle of 2008, when its first Socket AM3 processor manufactured on 45nm process technology will be announced, according to the makers.

 

[gOJDO]

Not in the first iterration, that's what I was talking about. Eventually, sure, but not until well into 2008.

AMD is going to have to get moving if they want to hold off intel in the server arena.

You are wrong, the first K8L CPUs will have HTT3.
http://www.hkepc.com/bbs/itnews.php?tid=679375&starttime=0&endtime=0
http://www.hkepc.com/bbs/itnews.php?tid=678954
http://www.hkepc.com/bbs/news.php?tid=679438&starttime=0&endtime=0
http://www.digitimes.com/mobos/a20061002PR207.html
http://www.digitimes.com/mobos/a20061003A2005.html
http://www.digitimes.com/NewsShow/Article_print.asp?datePublish=2006/10/03&pages=A2&seq=4

 

[Joe_The_Dragon]

But they are still sharing the same ram controller while AMD has on in EACH CPU.
Also are they using CSI for chipset to chipset links?

 

[ElMoIsEviL]

But they are still sharing the same ram controller while AMD has on in EACH CPU.
Also are they using CSI for chipset to chipset links?

Yes, Tigerton will not have an IMC (Integrated Memory Controller) such technology will first be introduced with the Itanium and then move down to the Xeon lineups.

It's not really useful for Desktop and Entry level server processors right now as memory bandwidth issues are for now a thing of the past. With Dual Channel DDR-2 support now becoming mainstream it's not really feasible for Intel to start using IMC's in all of their products.

BUT of course this changes in large SMP Xeon configurations. As more processors share the same memory bottlenecks start to appear. As to what Intel will do in the meantime to reduce this bottleneck is as of yet unknown. But one things for sure. Nobody, myself included, thought that Intel was able to introduce CSI so early. Looks like the ship really did steer into the right direction. In other words, AMD and Intel are in for a LONG fight... and we the consumers are about to reap the benefits.

 

[Joe_The_Dragon]

But they are still sharing the same ram controller while AMD has on in EACH CPU.
Also are they using CSI for chipset to chipset links?

Yes, Tigerton will not have an IMC (Integrated Memory Controller) such technology will first be introduced with the Itanium and then move down to the Xeon lineups.

It's not really useful for Desktop and Entry level server processors right now as memory bandwidth issues are for now a thing of the past. With Dual Channel DDR-2 support now becoming mainstream it's not really feasible for Intel to start using IMC's in all of their products.

BUT of course this changes in large SMP Xeon configurations. As more processors share the same memory bottlenecks start to appear. As to what Intel will do in the meantime to reduce this bottleneck is as of yet unknown. But one things for sure. Nobody, myself included, thought that Intel was able to introduce CSI so early. Looks like the ship really did steer into the right direction. In other words, AMD and Intel are in for a LONG fight... and we the consumers are about to reap the benefits.
can the Tigerton cpus talk to each other with out going thorough the chip set?

 

[qcmadness]

can the Tigerton cpus talk to each other with out going thorough the chip set?

I think so. To compete against AMD in server space, Intel needs its own direct connect architecture.

 

[godman]

Yes, Tigerton will not have an IMC (Integrated Memory Controller) such technology will first be introduced with the Itanium and then move down to the Xeon lineups.

It's not really useful for Desktop and Entry level server processors right now as memory bandwidth issues are for now a thing of the past. With Dual Channel DDR-2 support now becoming mainstream it's not really feasible for Intel to start using IMC's in all of their products.

2008 will see the nahlem uarch, and will have two different types of socket, soket H and socket B, one will allow the use of an IMC and one wil not. iassume then the socket that doesnt have an IMC will be or the desktoip user and the other or xeon processors. CSI will connect xeons to itanium and there you go...

New Nahlem uarch sockets

 

[godman]

Hmmmm..... [reads thread title]
This needs an appropriate image:

haha... :lol:

OMG! Careful! Intel might sue you for showing their pre launch advertising - before the processor is released

:lol: :lol: :lol:

 

[Parrot]

Socket AM2+ supports HT3. HT3 is backwards compatible with HT2. The K8L IMC supports both DDR2 AND DDR3!

The 65nm K8L which will come Q3 2007 will have DDR2 ODMC and will be sAM2 and sAM2+ compatible. The 45nm shrink of K8L will have DDR3 and DDR2 ODMC and will be sAM3 compatible.

Pay attention on the picture, "DDR2 with migration path to DDR3"




You have to distinguish between the socket support for DDR3 and the IMC support for DDR3. The reason AMD can so quickly change its plans and switch K8L from socket AM3 to socket AM2+ is because the IMC in K8L supports BOTH. That is what is meant by the phrase "DDR2 with migration path to DDR3". Otherwise think of the cost of producing new masks and dies for DDR3 support. This way, they just have to introduce a new socket, namely AM3, when they wish to migrate to DDR3 and don't have to redesign the CPU die because the IMC already supports DDR2 and DDR3. The only thing they have to change is the pin-out!

 

[ElMoIsEviL]

But they are still sharing the same ram controller while AMD has on in EACH CPU.
Also are they using CSI for chipset to chipset links?

Yes, Tigerton will not have an IMC (Integrated Memory Controller) such technology will first be introduced with the Itanium and then move down to the Xeon lineups.

It's not really useful for Desktop and Entry level server processors right now as memory bandwidth issues are for now a thing of the past. With Dual Channel DDR-2 support now becoming mainstream it's not really feasible for Intel to start using IMC's in all of their products.

BUT of course this changes in large SMP Xeon configurations. As more processors share the same memory bottlenecks start to appear. As to what Intel will do in the meantime to reduce this bottleneck is as of yet unknown. But one things for sure. Nobody, myself included, thought that Intel was able to introduce CSI so early. Looks like the ship really did steer into the right direction. In other words, AMD and Intel are in for a LONG fight... and we the consumers are about to reap the benefits.
can the Tigerton cpus talk to each other with out going thorough the chip set?

Well to me it seems all logical.. although speculation at this point. Logically Intel will use within their Chipsets something like ATi have used in their R520/580 architectures. This is of course the dispatch processor. Why do I believe this? Simple, no IMC and each Processor is said to have a dedicated CSI interconnect between each other BUT ALSO between each Processor and the Chipset (northbridge). This would indicate that each processor will need to go through a dispatch processor that will assign it access to the memory by priority. This will actually end up having the same affect it did with the R520/580.. improving efficiency and overall bandwidth.

But of course it's not as good as having your own IMC per processor... but Intel is not ready for that just yet.

So to answer your question with a definitive answer at this point is not possible. Intel has claimed CSI to be a point to point high speed serial interconnect therefore yes, it will connect each processor together circumventing the Chipset.. but as for memory access, they will all be accessing the memory pool VIA each a dedicated CSI interconnect with the chipset.. as for how this will be done.. well.. I've speculated in my post.. but it is as of yet unknown.

 

[qcmadness]

Well to me it seems all logical.. although speculation at this point. Logically Intel will use within their Chipsets something like ATi have used in their R520/580 architectures. This is of course the dispatch processor. Why do I believe this? Simple, no IMC and each Processor is said to have a dedicated CSI interconnect between each other BUT ALSO between each Processor and the Chipset (northbridge). This would indicate that each processor will need to go through a dispatch processor that will assign it access to the memory by priority. This will actually end up having the same affect it did with the R520/580.. improving efficiency and overall bandwidth.

But of course it's not as good as having your own IMC per processor... but Intel is not ready for that just yet.

So to answer your question with a definitive answer at this point is not possible. Intel has claimed CSI to be a point to point high speed serial interconnect therefore yes, it will connect each processor together circumventing the Chipset.. but as for memory access, they will all be accessing the memory pool VIA each a dedicated CSI interconnect with the chipset.. as for how this will be done.. well.. I've speculated in my post.. but it is as of yet unknown.

Tigerton will use Socket B????

Socket B will have IMC together with CSI.

 

[ElMoIsEviL]

Well to me it seems all logical.. although speculation at this point. Logically Intel will use within their Chipsets something like ATi have used in their R520/580 architectures. This is of course the dispatch processor. Why do I believe this? Simple, no IMC and each Processor is said to have a dedicated CSI interconnect between each other BUT ALSO between each Processor and the Chipset (northbridge). This would indicate that each processor will need to go through a dispatch processor that will assign it access to the memory by priority. This will actually end up having the same affect it did with the R520/580.. improving efficiency and overall bandwidth.

But of course it's not as good as having your own IMC per processor... but Intel is not ready for that just yet.

So to answer your question with a definitive answer at this point is not possible. Intel has claimed CSI to be a point to point high speed serial interconnect therefore yes, it will connect each processor together circumventing the Chipset.. but as for memory access, they will all be accessing the memory pool VIA each a dedicated CSI interconnect with the chipset.. as for how this will be done.. well.. I've speculated in my post.. but it is as of yet unknown.

Tigerton will use Socket B????

Socket B will have IMC together with CSI.

Unless Intel have changed their plans, Tigerton was set to introduce CSI but not an IMC. And the article I linked with regards to Clarksboro doesn't say anything about an IMC being taken out of Clarksboro and integrated into Tigerton.

Another thing most people don't know about Clarksboro is that it will feature a bus snoop filter with a 64MB cache. Not only is Intel putting a Large L2 and L3 Cache on Tigerton but also Cache on their chipsets.

This is said to cut the bandwidth needed on the bus and improve overal performance.

One things for sure, CSI looks to be quite promissing.

 

[qcmadness]

Unless Intel have changed their plans, Tigerton was set to introduce CSI but not an IMC. And the article I linked with regards to Clarksboro doesn't say anything about an IMC being taken out of Clarksboro and integrated into Tigerton.

Not good news for me.

 

[BaronMatrix]

I'm disappointed that the K8L won't be bringing HT3.0 with it while the Tigerton will be using CSI.

K8L WILL have HT3.0!!!

I was pretty sure K8L would be released with HT 2.0, as the AM2+ will be the only valid socket for it, and AM2+ only supports HT 2.0. I could be mistaken, and probably am. I'll go away and find some links..

No Barcelona will be released on Socket F. AM2+ is for the desktop dual core versions.

 

[ElMoIsEviL]

I'm disappointed that the K8L won't be bringing HT3.0 with it while the Tigerton will be using CSI.

K8L WILL have HT3.0!!!

I was pretty sure K8L would be released with HT 2.0, as the AM2+ will be the only valid socket for it, and AM2+ only supports HT 2.0. I could be mistaken, and probably am. I'll go away and find some links..

No Barcelona will be released on Socket F. AM2+ is for the desktop dual core versions.

I truly hope this isn't true... because if AMD's Quad Core K8L is to use a new socket then that means AMD's AM2 upgradeability just went completely down the shitter when compared to Intel's LGA775 supporting Core 2 Quad.

Are you sure about this?