Inside the Single-chip Cloud Computer
The name “Single-chip Cloud Computer” reflects the fact that the architecture resembles a scalable cluster of computers such as you would find in a cloud, integrated into silicon.
The research chip features:
24 “tiles” with two IA cores per tile
A 24-router mesh network with 256 GB/s bisection bandwidth
4 integrated DDR3 memory controllers
Hardware support for message-passing
In a sense, the SCC is a microcosm of cloud datacenter. Each core can run a separate OS and software stack and act like an individual compute node that communicates with other compute nodes over a packet-based network.
One of the most important aspects of the SCC's network fabric architecture is that it supports "scale-out" message-passing programming models that have been proven to scale to 1000s of processors in cloud datacenters. Though each core has 2 levels of cache, there is no hardware cache coherence support among cores in order to simplify the design, reduce power consumption and to encourage the exploration of datacenter distributed memory software models, on-chip. Intel researchers have successfully demonstrated message-passing as well as software-based coherent shared memory on the SCC.
Fine-grained power management is a focus of the chip as well. Software applications are given control to turn cores on and off or to change their performance levels, continuously adapting to use the minimum energy needed at a given moment. The SCC can run all 48 cores at one time over a range of 25W to 125W and selectively vary the voltage and frequency of the mesh network as well as sets of cores. Each tile (2 cores) can have its own frequency, and groupings of four tiles (8 cores) can each run at their own voltage.
http://techresearch.intel.com/articles/Tera-Scale/1826.htm