Intel users - all ignorant and uninformed!

[FatBurger]

Are you sure about the Tbird having copper? I remember talk of Dresden Tbirds having copper and the others not, but I think that rumor was laid to rest and copper interconnects came with the XP.

<font color=blue>If you don't buy Windows, then the terrorists have already won!</font color=blue> - Microsoft

 

[Guest]

About that Intel research on AMD's gate lenghs, personally, if AMD was able to use 0.13m technology so early on, then I would congratulate them on such good refinement and well researched. It got the Athlon core more than it wanted at 0.18m!

Eden, I'm not trying to make Intel look better than AMD, I'm just trying to guess why:

1) Throughbred is delayed by 3 month. End of Q1 most likely becomes end of Q2.
2) Reports on overclocking potential on early samples does not look too promising.
3) Thunderbird was 0.18 micron, XP was also reportedly 0.18 micron, but in reality below at various places. I believe AMD implemented this refined process for a purpose, not just to impress Intels engineers. I also assume, that it's more difficult to refine a 0.13 microm process in the same way.

As I said, my mission is not to bash AMD for fun, I'm just getting worried, as I was supposed to get myself a Throughbred last month and such a big delay, removes what was supposed to have given AMD superior performance. Instead Intel is working very hard to minimize the effect of Throughbred when it arrives. I just hope for AMD that the resulting product turns out to have great overcloking potential.

/Copenhagen

 

[Guest]

The gate lengths were smaller, this is sign of a refined process, NOT a direct relation to process size ...

Whatever, but I'm sure it all helps.

/Copenhagen

 

[eden]

Hey no frets man, I didn't want to mean you were bashing!
I do agree, there have been delays by AMD and yes, it is annoying. I am not very inclined on AMD's side these days too, because of this and the lack of recent action from their side, but no matter what happens, although this is off-topic, I will always beleive more in AMD's pride and worker enthusiasm than Intel's marketting...

--
For the first time, Hookers are hooked on Phonics!!

 

[castle]

1. The performance & frequency increase from Cu-mine to Tully benefit from copper interconnection in addition to 0.18-> 0.13 shrink. AXP-> T-Bred is purely a shrink, so I donot expect the improvement will be that impressive;
2. Tully has been updated several times before it reaches 1.4G (not 1.6 or 1.7 as nominated). Not in one shot! It will take some time before you see a mature and high freq. T-Bred.
Make sense?

 

[Matisaro]

Are you sure about the Tbird having copper? I remember talk of Dresden Tbirds having copper and the others not, but I think that rumor was laid to rest and copper interconnects came with the XP.

Dresden tbirds did in fact have copper, austin tbirds did not, sorry for not clarifying.

It is DIFFICULT IN THE EXTREME for a fab to use both copper and aluminum, so if dresden was set up for copper than while it is possible it also had aluminum as well, it is HIGHLY unlikely(copper is a hugely dirty process and it contaminates everything in a fab, and if copper gets in your alumimnum tools you have a problem).

Further evidence can be seen in the top speed of an austin tbird is about 1ghz, where a dresden tbird is 1.4ghz, the difference in fab quality can hardly explain a 40% difference in top speed on the same core. The answer is copper.

The Cash Left In My Pocket,The BEST Benchmark

 

[Matisaro]

Eden, I'm not trying to make Intel look better than AMD, I'm just trying to guess why:

1) Throughbred is delayed by 3 month. End of Q1 most likely becomes end of Q2.
2) Reports on overclocking potential on early samples does not look too promising.
3) Thunderbird was 0.18 micron, XP was also reportedly 0.18 micron, but in reality below at various places. I believe AMD implemented this refined process for a purpose, not just to impress Intels engineers. I also assume, that it's more difficult to refine a 0.13 microm process in the same way.

1) so was the northwood, was intel using .13 micron tech in its processors which caused it to be LATE as well?(moral, dont jump to conclusions)
2) if they are having trouble with the shrink OFCOURSE the first samples will not overclock well, which would also explain 1 above.( and I do believe they had a problem with the shrink, but texas techie hears they know whats wrong and have fixxed it, it does take 2 months + for a chip to get from start to finish in a fab)
3. Yes and no, the .13 CLASS gate lengths are not a direct relation to process size, and they DID give a performance advantage, but even if amd shrunk the process AND kept the same gatelength, the loss in top speed % would be VERY SMALL, the MAIN gains from a process shrink are lower heat and less current needed in the lines, period, gate lengths which are lower allow faster switching transistors, but very few transistors in a cpu are switching on and off near their max limit, the heat of the whole system keeps the clockspeed down low enough where thats not a major concern.
If I am making sense to you.

The Cash Left In My Pocket,The BEST Benchmark

 

[Matisaro]

1. The performance & frequency increase from Cu-mine to Tully benefit from copper interconnection in addition to 0.18-> 0.13 shrink. AXP-> T-Bred is purely a shrink, so I donot expect the improvement will be that impressive;
2. Tully has been updated several times before it reaches 1.4G (not 1.6 or 1.7 as nominated). Not in one shot! It will take some time before you see a mature and high freq. T-Bred.
Make sense?

1: this is true, and I agree which is why I estimate a 40% top speed gain for the axp instead of the tuallys 55%.
2: There were reports of the very first tuallys released hitting 1.6-1.7ghz, this was not a refined tually, the tually celersons dont hit as high, but I would attribute that to intel doing something to them personally.

When I made my prediction I took all these things into account, I also took into account amds superior gatelengths and their better design(as compared to the p3). So I stand by my prediction that the tbreds top speed will go up by 40-50% in the .13 micron shrink.




The Cash Left In My Pocket,The BEST Benchmark

 

[Guest]

So I stand by my prediction that the tbreds top speed will go up by 40-50% in the .13 micron shrink.

40% equals 2520 MHz
50% equals 2700 MHz

We are talking god old MHz here not AMD PR rating. Lets now convert these numbers to PR rating:

2520 MHz equals a PR 3280 rating !!!
2700 MHz equals a PR 3550 rating !!!

I that holds true, AMD will not even need the Hammer to finish off Intels current P4. AMD could then hold back the Hammer until Prescott turns up. Somehow I find those numbers hard to believe.

/Copenhagen

 

[Guest]

..., but very few transistors in a cpu are switching on and off near their max limit, the heat of the whole system keeps the clockspeed down low enough where thats not a major concern.

At a certain point, no matter what, you reach the max limit. If you find evidence, that a certain area of the die is reaching it's max before other parts, thus limiting the max obtainable frequency, then you will be able to rise performance if you fix those specific parts. I belive AMD refined their gates, or whatever, to raise the max obtainable frequency, but again, I'm just wild guessing.

/Copenhagen

 

[ath0mps0]

Actually:

AXP2100+ runs at 1733.333MHz:

40% gain = 1733.333 * 1.4 = 2426.667Mhz
50% gain = 1733.333 * 1.5 = 2600MHz

40% gain = (2426.667 - 1733.333) / 66.667 * 100 + PR2100 = PR3150+
50% gain = (2600 - 1733.333) / 66.667 * 100 + PR2100 = PR3400+

I thought a thought, but the thought I thought wasn't the thought I thought I had thought.

 

[Guest]

Try recalculate with XP2200+ as reference. AMD has announced they will release a XP2200+ before Throughbred turns up.

/Copenhagen

 

[Red_Pepper]

Good GOD! How many times does Mat have to re-iterate that his prediction for a Tbred 50-55% overclock is only on downbinned chips (he said nothing higher than 1800+)

The p4 1.6A is only 100Mhz off the speed the P4 debuted at originally (willy at 1.5Ghz). If we consider the AXP the Willy's counterpart, then it makes sense that the 1600+Tbred (second lowest debut speed) would be capable of the same overclock %age wise as the 1.6A p4.

BUT, considering the Tbred is not to market yet, maybe AMD is having trouble with yields.. its possible even a 16-1800+ Tbred isn't really capable of 2Ghz+ initially. Anything's possible, but no one in their right mind would suggest that a 2200+ will overclock 55%.


Mmmm... <font color=red>Red Hot</font color=red>

 

[Guest]

Good GOD! How many times does Mat have to re-iterate that his prediction for a Tbred 50-55% overclock is only on downbinned chips (he said nothing higher than 1800+)

Actually Red Hot Pepper, you are wrong. Matisaro has both talked about overclockability and top speed. Let me quote from another thread:

Matisaro wrote:
<font color=red>
MY main statement was that the core of the axp should see a 40-55% top speed increase from the shrink soley because of the shrink, and I listed many reasons for that to be true(the gain from the p3 shrink, the gain(although copper changes the relationship) from the p4 shrink.</font color=red>

SO WILL YOU <font color=red>CHILLY</font color=red> OUT FOR A MOMENT !

/Copenhagen

 

[Red_Pepper]

Oh wait,

I really didn't read of what you speak.
Sorry MOD, I thought this was another overclocking debate.

Either way, is AMD holding off on releasing Tbred so they can pump out a higher Mhz version off the bat? (instead of releasing 1800+A, 2000+A first) wAiting for the yields to be satisfactory?

Mmmm... <font color=red>Red Hot</font color=red>

 

[Red_Pepper]

Yeah MOD, lol, sorry

I had been reading the FatBurger challenge thread all the way through, and I clicked into this one and walked away for a sec. When I came back my memory must have lapsed...

Sorry! :redface:

Mmmm... <font color=red>Red Hot</font color=red>

 

[Matisaro]

40% equals 2520 MHz
50% equals 2700 MHz

We are talking god old MHz here not AMD PR rating. Lets now convert these numbers to PR rating:

2520 MHz equals a PR 3280 rating !!!
2700 MHz equals a PR 3550 rating !!!

They have ALREADY demoed a 2800+ chip, is another 200mhz so hard to believe>?>????



The Cash Left In My Pocket,The BEST Benchmark

 

[Matisaro]

I that holds true, AMD will not even need the Hammer to finish off Intels current P4. AMD could then hold back the Hammer until Prescott turns up. Somehow I find those numbers hard to believe.

This will be the END of the tbred, whereas the hammer supposedly will BEGIN at 3400, I can fully see a pr3000 tbred leading to the 3400 hammer.

And while the numbers may be hard to believe I have yet to hear a physical reason why that is.

The Cash Left In My Pocket,The BEST Benchmark

 

[Matisaro]

I belive AMD refined their gates, or whatever, to raise the max obtainable frequency, but again, I'm just wild guessing.

The refining of the gates was most likely a side effect of a good process, not a goal they set forth, when your fab is tight and you constantly meat your spc goals, you can begin to tighten specificatons, the gatelength is one of the first things you can tighten(that and gox thickness) without requiring retoooling, sure there is a benifit, but the benifit is not the same as the core gains from a die shrink would achieve.



The Cash Left In My Pocket,The BEST Benchmark

 

[Matisaro]

Yep, top speed, which MAY OR MAY NOT, be available immediatly, there will be tweaking there will be refinment, but I do stand by my TOPSPEED claims.

As for the overclockability over stock, I did only say the 55% would be for a downbinner amd, so pepper is right there.

The Cash Left In My Pocket,The BEST Benchmark

 

[Matisaro]

I think the delay is because their first steppings were not clocking well and they discovered a timing issue, they resolved the issue but it STILL TAKES 2-3 MONTHS for the corrected chips to come off the line.


I work(ed unemployed right now) in a fab, I know how these things work.

The gains from a process shrink are nearly universal independant from core design. The p3 gains 50-60% due to a shrink AND COPPER, the p4 gains about 50-60% from a shrink AND COPPER, the amd will gain about 40-50% from the shrink BUT THEY ALREADY HAVE COPPER.

LOok, this is an educated guess, I think I am right, but I really really want some logical reasoning which disagrees with me, only ray has tried(and was wrong) but I really want to get to the bottom of it and look at it logically.


There is one monkeywrench which is if the gatelengths DO have a huge impact, but everything I know about semiconductors(and I do know quite a bit, its my job) says this is not the case.

So I welcome a discussion and discourse, and I hope people can share their knowledge or things they have read which will possibly cause me to modify my theory to fit the data.

if anyone wants to chat real time Im in chat.classicrpg.com right now and I would love to discuss.


Matt

The Cash Left In My Pocket,The BEST Benchmark

 

[eden]

So let me get this straight:
The gate lenghs that were 0.13m (possibly) in the Palomino mostly contributed to a little more in clockspeed, right? However they were independant to the lower heat issues, which are mostly and majorly part of the redesign, right?
If that is so, then I don't see why 40-50% higher clockspeed wouldn't happen, because gate lenghs had little impact, and since Northwood is also demonstrating a similar pattern to P3 (maybe a slightly higher max clock speed due to NetBurst), I do not see how Athlons would die out so early on.

BTW is Fugistsu a supplier for fabs for AMD's chips? If not, then what chip fabs you were mostly working in?

Also this has been teasing me:
Would the max clock speed change if a company converted from 0.18m and skipped directly to 0.09m? I was wondering maybe if they would pass through the 0.13m first, they would squeeze to max, instead of stand by theoretical speeds, and then jump to 0.09m, thus in total from 0.18m times to 0.09m the max clock speed was higher than the one if they had skipped through 0.13m and went directly to 0.09m.

--
For the first time, Hookers are hooked on Phonics!!

 

[Matisaro]

So let me get this straight:
The gate lenghs that were 0.13m (possibly) in the Palomino mostly contributed to a little more in clockspeed, right? However they were independant to the lower heat issues, which are mostly and majorly part of the redesign, right?

Yep

BTW is Fugistsu a supplier for fabs for AMD's chips? If not, then what chip fabs you were mostly working in?

Fujitsu was a flash partner with amd, although our fab didnt do logic we did flash and dram, the process is the same but logic has more metal layers and is more complex(but less dense).

The Cash Left In My Pocket,The BEST Benchmark

 

[Matisaro]

Would the max clock speed change if a company converted from 0.18m and skipped directly to 0.09m? I was wondering maybe if they would pass through the 0.13m first, they would squeeze to max, instead of stand by theoretical speeds, and then jump to 0.09m, thus in total from 0.18m times to 0.09m the max clock speed was higher than the one if they had skipped through 0.13m and went directly to 0.09m.

Assuming you had no issues the net gain would be the same, a process will top out at a certain speed on a process size regardless of refinement. (although refinement may gain you some top speed it will always be bested by a shrink.

The Cash Left In My Pocket,The BEST Benchmark

 

[eden]

So what differenciates refinement from process/die shrink?

--
For the first time, Hookers are hooked on Phonics!!