News Intel's 18A and TSMC's N2 process nodes compared: Intel is faster, but TSMC is denser

[JayNor]

Intel has already presented numbers of 15% better performance per watt for their RibbonFET vs FinFET.

GAA is also said to reduce leakage current.

THW reported on BSPD : "increase clock speed by over 6%, reduced IR voltage droop by 30%, and increased cell utilization over large areas of its E-core die to over 90%"

... so, TSM won't see the BSPD advantages for a couple of years.

The IR voltage droop 30% reduction looks interesting. Any possibility Intel takes advantage of that to simply run the chips at lower voltage?

 

[bit_user]

N3B ... was widely panned as bringing the worst generational node uplift in TSMC's history.

LOL, according to whom? Because, whoever it was, I guess they never heard of 12FFN, which is only like 3% denser than 16FF.

Anyway, definitely expect to see more underwhelming uplifts, because that's what the end of Moore's Law looks like.

It was equally sad to see Intel dump 20A for Arrow Lake (at least i3/i5) and go for N3B, not N3E.

Intel needs quite large production volume, compared to TSMC's other customers. The 3nm wafer allocation it's been using was purchased years ago, probably before N3E existed.

 

[thestryker]

There was never N3, it always launched as N3B for whatever reason, and was widely panned as bringing the worst generational node uplift in TSMC's history. It was always amusing how Apple with their deep pockets rushed into 3nm just for bragging rights and didn't care about the higher wafer cost for minimal improvement over N4P.

Apple always uses high density which means N3 was actually a very big upgrade and N4P was never on the table.

It was equally sad to see Intel dump 20A for Arrow Lake (at least i3/i5) and go for N3B, not N3E.

While they'd never publicly admit it Intel 4 appears to have been an anchor dragging on IFS. It was important for developmental purposes, but probably never should have been used for a high volume product. Intel 3 is the long term node and Intel won't be shifting volume out of it any time soon. Relatively speaking they have very few EUV machines which means locking them in can be a problem longer term.

So long as 18A was on production track it makes sense to not use 20A for any volume products even if short term it costs Intel more money. Had they moved ahead with 20A the machines would have been locked in for a couple of years to ensure ongoing volume. This would have likely required somewhere in the 10s of thousands of wafers which could otherwise be tasked with 18A.

 

[bit_user]

Apple always uses high density which means N3 was actually a very big upgrade and N4P was never on the table.

For Apple, the priority is always on power efficiency. That means they shouldn't be as dependent on high-performance cells as Intel or AMD.

 

[Pierce2623]

Apple and Intel. Lunar Lake uses TSMC N3P. But there's also an N6 die and the Intel 22nm interposer, whereas Apple's chips are mostly monolithic N3E. I think that still gives Intel the edge though; N3P is a more advanced node than N3E.
https://www.anandtech.com/show/1883...n-schedule-n3p-n3x-deliver-five-percent-gains

As bit_user already pointed out that is strictly rumor as of now.

 

[Pierce2623]

Apple always uses high density which means N3 was actually a very big upgrade and N4P was never on the table.

While they'd never publicly admit it Intel 4 appears to have been an anchor dragging on IFS. It was important for developmental purposes, but probably never should have been used for a high volume product. Intel 3 is the long term node and Intel won't be shifting volume out of it any time soon. Relatively speaking they have very few EUV machines which means locking them in can be a problem longer term.

So long as 18A was on production track it makes sense to not use 20A for any volume products even if short term it costs Intel more money. Had they moved ahead with 20A the machines would have been locked in for a couple of years to ensure ongoing volume. This would have likely required somewhere in the 10s of thousands of wafers which could otherwise be tasked with 18A.

As far as I know both Intel 4 and Intel 20a were both just considered almost experimental steps to get to the main nodes. If I remember correctly, they didn’t even receive all the libraries for a full SoC but only compute tiles.

 

[TheSecondPower]

As bit_user already pointed out that is strictly rumor as of now.

Intel does use an N6 die and a 22 nm-based interposer die in Lunar Lake, but I was wrong about N3P. Instead of N3P the compute tile is N3B; as someone here pointed out that's on Intel Ark. What Apple uses might be rumor, but Apple getting exclusive access to the newest nodes and using them is not, so at least some M4 chip must be using N3E or N3P.

 

[shady28]

As far as I know both Intel 4 and Intel 20a were both just considered almost experimental steps to get to the main nodes. If I remember correctly, they didn’t even receive all the libraries for a full SoC but only compute tiles.

Yes, Intel 4 and 20A were supposed to be learning steps for high power Intel chips only. Intel 4 morphed into Intel 3 and Intel 3 was to be an IFS node, while 20A was to morph into 18A IFS.

Intel's main advantage right now is being first to market with 2nm class by about 6-12 months, and the simple fact that their main competition (AMD) will likely be limited to some N3 node for the next 2 years as Apple typically takes up all the capacity for the first year TSMC has a node.

So Intel has a roughly 18 month window (mid 2025 - early 2027) to utilize their node advantage.

Lunar Lake is a very good product and I think Panther Lake will be significantly better, so by all rights they should dominate the laptop market once that launches (which is several times the size of desktop). Ofc, price is a big factor, and so far the Lunar Lake laptops have been very pricey.

Granite Rapids and Sierra Forest are also very competitive now, with Granite Rapids taking the #1 spot in Phoronix server benchmarks for HPC / AI. This is probably why Musk used Intel for servers in his new AI datacenter.

 

[bit_user]

As far as I know both Intel 4 and Intel 20a were both just considered almost experimental steps to get to the main nodes.

Using them for products makes them non-experimental. Pretty much since it was announced, Intel told us Meteor Lake would use Intel 4. Same thing with Arrow Lake and Intel 20A. So, these weren't late tactical decisions, but rather part of the plan.

 

[bit_user]

What Apple uses might be rumor, but Apple getting exclusive access to the newest nodes and using them is not, so at least some M4 chip must be using N3E or N3P.

M3 uses N3B, which makes comparisons between it and Lunar Lake very interesting (hint: it's not very flattering for Lunar Lake!)

https://www.notebookcheck.net/Intel...its-everyday-efficiency-is-good.893405.0.html
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The M4 uses N3E and also has more microarchitecture improvements than the M3 did.

The M5 is rumored to use N3P:

https://www.tomshardware.com/pc-com...tion-using-tsmc-performance-enhanced-3nm-node
​

 

[bit_user]

Yes, Intel 4 and 20A were supposed to be learning steps for high power Intel chips only. Intel 4 morphed into Intel 3 and Intel 3 was to be an IFS node, while 20A was to morph into 18A IFS.

All 4 nodes were on their roadmap ever since they had a roadmap which included Intel 3 or 18A.

(AMD) will likely be limited to some N3 node for the next 2 years as Apple typically takes up all the capacity for the first year TSMC has a node.

AMD already started using a N3-family node last year, with the Zen 5C chiplet. I'm not sure which.

I think I saw rumors of AMD using a N2 node for Zen 6, in 2026.

Lunar Lake is a very good product and I think Panther Lake will be significantly better, so by all rights they should dominate the laptop market

All Lunar Lake models (except the 288V) have a base power of 17W. Panther Lake is being leaked to have a base power of 25W, and yet it's limited to just 4P + 8E cores. IMO, that's not a great move for a Lunar Lake replacement.

https://www.tomshardware.com/pc-com...-leaked-specs-point-to-substantial-power-draw
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Granite Rapids and Sierra Forest are also very competitive now,

Um, no. Sierra Forest was competitive against Zen 4C, but not Zen 5C.

with Granite Rapids taking the #1 spot in Phoronix server benchmarks for HPC / AI. This is probably why Musk used Intel for servers in his new AI datacenter.

Granite Rapids is fast in AI only because of AMX. On non-AI workloads, it falls behind Zen 5C. I'm sure most of the cloud server market isn't running AI on CPUs.

 

[thestryker]

All Lunar Lake models (except the 288V) have a base power of 17W. Panther Lake is being leaked to have a base power of 25W, and yet it's limited to just 4P + 8E cores. IMO, that's not a great move for a Lunar Lake replacement.

​

https://www.tomshardware.com/pc-com...-leaked-specs-point-to-substantial-power-draw​

The 4P/4LPE/4Xe3 part is 15W base power, but what stands out to me most is that there are only 4 and 12 Xe3 core IGP configurations. That part could only really be a solid LNL replacement if Celestial is that much better.

 

[dipique]

Team blue has underperformed consistently, for a decade... To my dismay. I'll eat Pat's retirement golf hat if they actually manage to get attractive hardware to market before 26. And i don't mean: "Damn the icebergs, full amps ahead!"

I mean, lunar lake looks pretty damn good. If you don't mind the price.

 

[Pierce2623]

Using them for products makes them non-experimental. Pretty much since it was announced, Intel told us Meteor Lake would use Intel 4. Same thing with Arrow Lake and Intel 20A. So, these weren't late tactical decisions, but rather part of the plan.

I mean experimental in the sense that they’re designed from the outset to only have the libraries necessary to be capable of producing compute tiles rather than an entire SoC, whereas 18a and Intel 3 both have the full complement of libraries. Basically each one was considered a necessary step to get to where they wanted technologically, but never targeted to be their mainline “do it all” nodes.

As an aside, Intel needs to more worried about how 18a will compete against TSMC a16 set to roll in 2026 since they only currently expect 14a in 2027. Without Pat there, I think they’ll spend the bare minimum on node R&D to get the government money and 14a probably won’t be ready in 2027. TSMC a16 has ALL the bells and whistles. Backside power delivery, nanosheet transistors, and supposedly it will even maintain the good sram scaling of n2.

 

[bit_user]

I mean experimental in the sense that they’re designed from the outset to only have the libraries necessary to be capable of producing compute tiles rather than an entire SoC, whereas 18a and Intel 3 both have the full complement of libraries. Basically each one was considered a necessary step to get to where they wanted technologically, but never targeted to be their mainline “do it all” nodes.

Intel 4 and Intel 3 appear to differ in much more substantial ways than which types of cells they have in their libraries. Just look at the amount of improvement in Meteor Lake Refresh, where the CPU die was ported to Intel 3. Ignore the fact that Intel is calling it "Arrow Lake" - it's really not.

https://www.notebookcheck.net/Intel...iled-for-thin-and-light-laptops.941408.0.html
​

Without Pat there, I think they’ll spend the bare minimum on node R&D to get the government money

Huh? That's not how it works.

 

[Pierce2623]

Intel 4 and Intel 3 appear to differ in much more substantial ways than which types of cells they have in their libraries. Just look at the amount of improvement in Meteor Lake Refresh, where the CPU die was ported to Intel 3. Ignore the fact that Intel is calling it "Arrow Lake" - it's really not.

​

https://www.notebookcheck.net/Intel...iled-for-thin-and-light-laptops.941408.0.html​

​

Huh? That's not how it works.

Intel 3 is definitely a development of Intel 4. We don’t say n5 is radically different from n7 just because Zen4 gained more click speed than expected…

As far as the government money it works like: “you start a facility to build X and we’ll pay Y”. However they can’t just wait for the company to do it then give them the money. They get paid certain amounts when they pass certain benchmarks. Without Pat there, I believe there’s a good chance they’ll just do what’s necessary to meet the benchmarks on time, rather than getting the fab opened as quickly and successfully as they have the monetary ability to do, like they were doing under Pat. Pat was one of the VERY few people at the top that truly believed in the fab group. I think I’ll probably be proven somewhat correct when 18a comes out swinging but 14a will get tons of standard Intel delays. There’s virtually zero chance they’re new CEO will be as bullish on fabs.

 

[bit_user]

We don’t say n5 is radically different from n7 just because Zen4 gained more click speed than expected…

N5 is a different node family than N7. Zen 4 is a different microarchitecture than Zen 3. Thus, Ryzen 7000 (i.e. the chiplet ones) vs. the corresponding Ryzen 5000 can't really tell you much about N5 vs. N7.

What makes Meteor Lake Refresh interesting is that it's the same microarchitecture on two different nodes.

As far as the government money it works like: “you start a facility to build X and we’ll pay Y”. However they can’t just wait for the company to do it then give them the money. They get paid certain amounts when they pass certain benchmarks. Without Pat there, I believe there’s a good chance they’ll just do what’s necessary to meet the benchmarks on time,

CHIPS has claw-back provisions. I don't know how extensive they are, but for instance it has one where if a company makes a windfall profit, then you have to pay it back. There might be additional conditions saying that if you don't put in the amount of investment on your end that you promised, then you don't qualify for further rounds. Remember: they tried to design the program to stimulate capacity building, and not waste taxpayer money.

Pat was one of the VERY few people at the top that truly believed in the fab group. I think I’ll probably be proven somewhat correct when 18a comes out swinging but 14a will get tons of standard Intel delays. There’s virtually zero chance they’re new CEO will be as bullish on fabs.

I'm sure everyone cares about the fab. They want to split up the company, so they know they need to keep investing in the fabs or else IFS won't be able to IPO and no one will want to buy it.

 

[Rob1C]

Too bad IMEC wasn't compared.

https://www.asml.com/en/news/press-releases/2024/asml-imec-opening-high-na-euv-lithography-lab
https://www.asml.com/en/products/euv-lithography-systems/twinscan-exe-5000
https://www.imec-int.com/en/articles/imec-puts-complementary-fet-cfet-logic-technology-roadmap

 

[bit_user]

Too bad IMEC wasn't compared.

IMEC is basically just a research organization. They don't have any production that you could even use, in any sort of comparison. As far as I understand, they're sort of like an IP factory and contract R&D firm for the rest of the semiconductor industry, who then base their production nodes & machinery on IMEC's findings.

https://en.wikipedia.org/wiki/IMEC
​

 

[thestryker]

Too bad IMEC wasn't compared.

IMEC is useless in a conversation about actual products because they're a pure R&D organization that doesn't make anything.

 

[Rob1C]

IMEC is basically just a research organization. They don't have any production that you could even use, in any sort of comparison. As far as I understand, they're sort of like an IP factory and contract R&D firm for the rest of the semiconductor industry, who then base their production nodes & machinery on IMEC's findings.

​

https://en.wikipedia.org/wiki/IMEC​

​

IMEC is useless in a conversation about actual products because they're a pure R&D organization that doesn't make anything.

Is there a problem when you don't get through the first paragraph of the first link.

> "... After a build and integration period of years, the Lab is ready to provide leading-edge logic and memory chip makers, as well as advanced materials and equipment suppliers access to the first prototype High NA EUV scanner (TWINSCAN EXE:5000) and surrounding processing and metrology tools.".

My point was to compare leading edge equipment that is available and in use, possibly by the very companies mentioned, with what is currently in use by them.

What do they call it when you interpret what is said in such a manner that you offer a negative feedback rather than expending the effort to see how the idea is useful.

 

[bit_user]

Is there a problem when you don't get through the first paragraph of the first link.

> "... After a build and integration period of years, the Lab is ready to provide leading-edge logic and memory chip makers, as well as advanced materials and equipment suppliers access to the first prototype High NA EUV scanner (TWINSCAN EXE:5000) and surrounding processing and metrology tools.".

My point was to compare leading edge equipment that is available and in use, possibly by the very companies mentioned, with what is currently in use by them.

Yes, I actually saw that. I'm sure it's for R&D purposes, not production. For instance, when Intel wants to test out some new idea for fabricating wires on a new node, they need to actually try it on modern equipment. In order to do that, they probably design some simple test circuits they can use to measure its electrical parameters and manufacturability. Hence, it's incredibly valuable for a semiconductor R&D lab to have access to the latest lithography equipment.

https://www.tomshardware.com/pc-com...chip-packaging-and-interconnects-at-iedm-2024
​

There's a lot more that goes into a manufacturing node that just the equipment you use. Intel, TSMC, Samsung, and others routinely spend billions of dollars taking the ideas and research from places like IMEC and developing them into an actual production node with optimized cell libraries and support for the kinds of software tools you need in order to actually design a working chip. If it were a simple matter of the lithography equipment, then there'd be virtually no difference between most of the fabs, most of the time.

What do they call it when you interpret what is said in such a manner that you offer a negative feedback rather than expending the effort to see how the idea is useful.

You complained that the article didn't compare it to IMEC. We just tried to explain why such a comparison can't be done.

I can't speak for @thestryker, but if you want to discuss ideas, I'm here for that. But I don't coddle any egos or walk on eggshells, because tech doesn't care about your feelings and details do matter. Engineering is humbling in that way - it's much less of a "yes, and ..." exercise and more of a "no, but ..." one.

 

[thestryker]

My point was to compare leading edge equipment that is available and in use, possibly by the very companies mentioned, with what is currently in use by them.

Nobody is using High-NA for production and it likely won't be seen until Intel's 14A in 2027 should that stay on track. Intel had the only operational Twinscan 5000 outside of ASML as of the last public updates and this is for R&D (they have orders for 5200s). TSMC and Samsung only have purchases for research (this likely means one 5000) which means they're even further out.

What do they call it when you interpret what is said in such a manner that you offer a negative feedback rather than expending the effort to see how the idea is useful.

Perhaps the issue is just that you lack the underlying knowledge of the industry in question. IMEC isn't applicable to this topic as they do not volume produce anything and do not make full nodes. They do research and license technologies so if there's something specific you want to bring to the table by all means that's adjacent to this topic.