Intel had problems solving the 10nm multi-patterning, but persevered.
In parallel they had a group working on 7nm with EUV, but ASML only began producing a machine that meets their high volume requirements in q3 of 2019, and has only built 9 of them to date.
In parallel, Intel also developed Sunny Cove core, wifi6, thunderbolt3, gen11 graphics, optane memory controller, optane ssds, nnp chips, dlboost avx512 instructions ... so it isn't like they did nothing while 10nm multi-patterning problems were being solved.
This performance improvement info on Optane is more interesting than the delay. I hadn't seen this before ... only speculation about the density improvement. Is this a big deal?
"... are designed to deliver three times the throughput while reducing application latency by four times ..."
The Cooper Lake and Ice Lake Server roadmap details list Barlow Pass support as a feature. Did something change in the Optane memory interface?