News Intel's First Discrete GPU, the DG1, Listed with 96 EUs

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Though I have yet to find a complete EU ISA reference, I've so far only seen them discuss dot product instructions, which is not something you find in either Nvidia or AMD.

What I've been writing about in the last 10 posts isn't about what is or isn't in the ISA. There is no "cross product" instruction, but swizzling float3s make it trivial on GPUs where swizzling is free.

 

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swizzling float3s make it trivial on GPUs where swizzling is free.

It's funny how we only started talking about that, after you singled out lane-swizzling as an operation that scales poorly. Now, you say it's free?

 

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It's funny how we only started talking about that, after you singled out lane-swizzling as an operation that scales poorly. Now, you say it's free?

Free programmer-wise.

Silicon-wise, you already have a monstrous mux to get N P-wide values out of the M-deep register file where N is the maximum number of concurrent register reads or write, M is the register file depth and P is the width. A 4x4 swizzle mux that operates within a single pair of P-wide float3/4 operands is insignificant next to that.