Introducing Intel's 14nm Node and the Broadwell Processor

[dovah-chan]

Nerds

 

[RedJaron]

I am pretty sure the article is correct

You are dealing with 2 dimension calculation,
so assume dies are squares, area shrink would be approx.:
(sqrt(130) - sqrt(82) )^2 + (((sqrt(130) - sqrt(82) ) x sqrt(82)) x2)
= (11.4018 - 9.0554)^2 + (((11.4018 - 9.0554) x 9.0554) x2)
= 2.3464^2 + ((2.3464 x 9.0554) x2)
= 48.0008mm2 lost

(130 - 48.0008) / 130 = 0.6308 = 63.08%

so you do lose 63% surface area going from 130mm2 to 82mm2

I think my math is right (been a while since I done geometry)
Please correct me if I am wrong.

The math is correct ( until the very last line, ) so your conclusions are not. 82 is 63% of 130, but that is the number retained, not lost. You've lost 48 sqmm, 48 is 37% of 130, therefore you've lost 37% of the area. You're also using a very convoluted way of simply taking area 1 and subtracting area 2: 130 - 82 = 48. I see your method, you've overlapped two squares of differing size, treating one common corner as an anchor point, and then added up the void areas ( two rectangles and a square. ) This would be necessary if you didn't already know the dimensions, but we do.

It doesn't matter what the actual length or height of the dies are. We've been given a total area of silicon and that area is what is being compared. It's a simple matter of Area1 x Percent = Area2. That leaves you with either 130 / 82 or 82 / 130. Case one = 158%, case 2 = 63%. Taking those percentages and subtracting 100% will give you a difference in size as a percent ( if the result is negative, then it's smaller. ) That leaves 58% and -37%.

The review simply used the wrong words, or put the chips in the wrong order in the sentence. It would have been correct to say that Broadwell-Y's size is 63% of Haswell-Y or that Haswell-Y has been scaled down to 63% of its former size. You could say Haswell is 158% of Broadwell or that it's 58% larger than Broadwell. On the flip side, you can say Broadwell is 63% of Haswell or that it's 37% smaller, or that Haswell has been reduced 37%.

Nerds

Hey, I [strike]wasted[/strike] paid lots of money for that math degree, I'm going to use it, damn it!

 

[wingofword]

I am pretty sure the article is correct

You are dealing with 2 dimension calculation,
so assume dies are squares, area shrink would be approx.:
(sqrt(130) - sqrt(82) )^2 + (((sqrt(130) - sqrt(82) ) x sqrt(82)) x2)
= (11.4018 - 9.0554)^2 + (((11.4018 - 9.0554) x 9.0554) x2)
= 2.3464^2 + ((2.3464 x 9.0554) x2)
= 48.0008mm2 lost

(130 - 48.0008) / 130 = 0.6308 = 63.08%

so you do lose 63% surface area going from 130mm2 to 82mm2

I think my math is right (been a while since I done geometry)
Please correct me if I am wrong.

The math is correct ( until the very last line, ) so your conclusions are not. 82 is 63% of 130, but that is the number retained, not lost. You've lost 48 sqmm, 48 is 37% of 130, therefore you've lost 37% of the area. You're also using a very convoluted way of simply taking area 1 and subtracting area 2: 130 - 82 = 48. I see your method, you've overlapped two squares of differing size, treating one common corner as an anchor point, and then added up the void areas ( two rectangles and a square. ) This would be necessary if you didn't already know the dimensions, but we do.

It doesn't matter what the actual length or height of the dies are. We've been given a total area of silicon and that area is what is being compared. It's a simple matter of Area1 x Percent = Area2. That leaves you with either 130 / 82 or 82 / 130. Case one = 158%, case 2 = 63%. Taking those percentages and subtracting 100% will give you a difference in size as a percent ( if the result is negative, then it's smaller. ) That leaves 58% and -37%.

The review simply used the wrong words, or put the chips in the wrong order in the sentence. It would have been correct to say that Broadwell-Y's size is 63% of Haswell-Y or that Haswell-Y has been scaled down to 63% of its former size. You could say Haswell is 158% of Broadwell or that it's 58% larger than Broadwell. On the flip side, you can say Broadwell is 63% of Haswell or that it's 37% smaller, or that Haswell has been reduced 37%.

Nerds

Hey, I [strike]wasted[/strike] paid lots of money for that math degree, I'm going to use it, damn it!

you are right, I didn't think if it that way
like I said, been a while since I use this stuff

 

[Joao Ribeiro]

Facepalm! x86 is the overall ISA of Intel and AMD. It's the basic instruction set both carry (16-bit and 32-bit. AMD beat intel to market with their version of x64, though there are a lot of design flaws which at some later date will need to be removed). Both companies create instruction set extensions to go on top of the basic x86 package, but AMD CPUs and Intel CPUs are both x86 architecture, named for the 8602 processor from which it evolved.

8602 LOOOOOOOOOOOOOOOOOOOOOL

8086, and 8088 were the fhe forefathers. 8602?? For petes sake, 8602 is a RISC CPU the x86 comes from a CISC CPU, come on, have mercy.

 

[Doughnutnator]

I just bought a freaking 4570, screw this! Anyways it's nice to see the work Intel is doing.

 

[The3monitors]

When this is released than This is when my 3770k will be obsolete and be used as a secondary media renderer

 

[patrickjp93]

I'm shocked at how people complain about a 5% (overall) ipc improvement, when the reality is for scientific computing that 5-cycle to 3 can yield 25% or more improvement.

Most people do not do scientific computing in their everyday life and shrinking the integer multiply from 5 cycles to 3 cycles makes no difference performance-wise since the operation is pipelined and gives you one result per cycle regardless of how many clock ticks it takes. Unless your scientific application makes a conditional branch or random memory access based on that multiplication all the time, multiply latency should not matter much.

Most scientific algorithms I know of tend to apply multiply-add operations to large arrays and matrices before applying any logic. The multiply latency hit would be something that matters once per thousands if not millions of multiply operations in properly optimized code so the shorter latency would improve performance of those algorithms by less than 0.1%.

floating point multiply & divide. Integer was already 1 cycle. And that would go into the multiply-add operation as well.