sykozis :
You really don't know enough about the computer industry to make the statements you have. Due to laws, Intel has very little control over the total cost of a computer (Anti-Trust and consumer protection laws). Intel can't "completely destroy" AMD as they are the only processor companies competing in the desktop market. Intel also competes against VIA in the embedded market, where AMD used to compete as well, but VIA has no effect on the desktop market. Until ARM processors or VIA enter the desktop market, Intel legally can't do anything to "completely destroy" AMD. In other words, Intel has to make sure AMD can compete in some capacity....
Intel actually has a pretty large amount of control over the price of a standard computer as the CPU is one of the most expensive parts of the computer, and it is the only piece of computer hardware that is not essentially a commodity. You have Microsoft to thank for that one as the Windows monopoly locked in Intel's x86 architecture as THE only CPU architecture anybody wanted for consumer machines. It takes access to Intel's patents to make an x86 CPU and Intel holds onto those with a death grip. Only Intel, AMD and VIA make x86 CPUs, and AMD and VIA were embroiled in massive, recurrent lawsuits to be able to do so. And even with that, VIA's licensing term will be up soon and the only reason Intel let VIA make x86 CPUs is that Intel needed some of VIA's patents. Apparently those VIA patents will expire soon and I predict VIA will be up a creek without a paddle when the current x86 licensing term is up.
What will break Intel's monopoly is the Windows-x86 hegemony breaking. As much as they suck, smartphones and tablets running non-x86/non-Windows and/or Web-based programs is what is going to do this. Once "Windows" and "computing" are no longer synonymous, Intel will be forced to compete with the multitude of non-x86 CPU makers instead of just AMD and VIA. I'd love to see Intel take on somebody more their own size like Samsung. That would be a good battle, I'll bring the popcorn!
The Conroe architecture had shorter pipelines and higher IPC than the K8 (9-12IPC) or K10 architecture. Conroe had lower clocks speeds compared to the Northwood or Prescott architectures based on NetBurst. NetBurst had long pipelines, which catered to high clock speeds but suffered from low IPC (4-6) as a result. AMD's "Bulldozer" architecture is very similar to Intel's NetBurst architectures in that is has long pipelines and thus, low IPC.
Conroe actually had a longer pipeline than K8 and K10. Conroe and Nehalem had 14 stages and K8/K10 had 12 stages. We don't know how many Bulldozer has, except that it is more than 12. I'd bet somewhere around 20 based on its frequency and behavior in certain applications. I've also seen no figures given for Sandy Bridge, except that it has more than Conroe/Nehalem. My guess is 15-17.
Also, the actual IPC of any of those CPUs is well under 3, generally on the order of 1.0-1.5. You never get to keep the pipeline 100% full all of the time and retire the maximum theoretical number of instructions every clock cycle. Pipeline stalls due to dependencies, branch mispredictions, and cache misses prevent you from reaching maximum performance. Otherwise, we'd all be using massively wide, in-order units like Itanium. It has a maximum IPC of 8 compared to 3-4 for current x86 CPUs. The reason that long pipeline can hinder performance is that you may have to completely flush it and then refill if you mispredict a branch, etc. Your 20-stage 4.0 GHz CPU takes longer to refill the pipeline and finish operations than a 10-stage 2.5 GHz CPU. However, pipelining is not all bad, you can run the CPU much faster and get much greater throughput with a full pipeline with a long-pipelined, high-clocked CPU than a short-pipelined, low-clocked one. It's just that delicate balance that you have to reach, and it keeps changing. The better you get at minimizing stalls and misses (better branch prediction, bigger/better caches), the longer you can make the pipeline without seriously degrading performance in less than optimal code and the higher peak performance your CPU can attain. That's why we are seeing the number of stages slowly increase, from 10 in the PIII/Athlon to closer to 20 in Sandy Bridge without going the way of the P4's poor performance.