News Japanese Professor Sues Intel For Infringing Patent Involving FPGAs, SoCs

[Admin]

As per a new report, Intel finds itself in another patent infringement case, this time involving its FPGA and SoC chips that use ALMs.

Japanese Professor Sues Intel For Infringing Patent Involving FPGAs, SoCs : Read more

 

[spentshells]

sounds like he deserves it

 

[Geef]

Sadly this is one of those stories where we will probably never hear anything about it ever again. Intel will make an agreement with a NDA attached and throw the guy a bone.

The end.

 

[derekullo]

Did he recently come out of his coma in 2022?

If some one blatantly uses your patent and you don't file an infringement lawsuit within six years of the date of the alleged infringement you aren't able to recover any money.

https://www.nolo.com/legal-encyclop...-in-which-to-sue-for-patent-infringement.html

Very convenient he waits to the nearly 6 year mark before making a complaint if he is claiming it started in 2016 Q3.

 

[InvalidError]

This isn't much of a discovery: he basically patented wrapping a bunch of smaller LUTs in mux/selector logic.

Very convenient he waits to the nearly 6 year mark before making a complaint if he is claiming it started in 2016 Q3.

The patent was awarded in 2004. That's 18 years ago.

Xilinx and Altera have been using 6-inputs LUTs that can be configured between a handful of memory configuration and predefined functions since 2008. Shouldn't have taken him 14 years from infringement to sue. Maybe he gave up going after Xilinx and Altera, then decided to have another go at it once they got gobbled up by AMD and Intel.

 

[jkflipflop98]

I hope he gets buried with legal costs once he loses.

 

[TerryLaze]

Xilinx and Altera have been using 6-inputs LUTs that can be configured between a handful of memory configuration and predefined functions since 2008. Shouldn't have taken him 14 years from infringement to sue.

Maybe the original deal with xilinx altera was for an exclusive non-transferable patent.
Intel bought altera in 2016, so 6 years not 14.

 

[KyaraM]

Maybe the original deal with xilinx altera was for an exclusive non-transferable patent.
Intel bought altera in 2016, so 6 years not 14.

He held the patent until 2014, and they bought the company in 2016. That's a two-year lag in which any chip developed would not fall under his claim. If they held an agreement, then any new chip with his design after Intel bought the company would have been long out of his claim. Also, in a case like that, you approach the company immediately for renegotiations if you do have a valid claim, not wait 6 or more years for it. This here is kinda scummy.


Also, no original deal mentioned, though there likely was one. Else, it makes even less sense to sue now and won't bear any fruit, either.

 

[TerryLaze]

He held the patent until 2014, and they bought the company in 2016. That's a two-year lag in which any chip developed would not fall under his claim. If they held an agreement, then any new chip with his design after Intel bought the company would have been long out of his claim. Also, in a case like that, you approach the company immediately for renegotiations if you do have a valid claim, not wait 6 or more years for it. This here is kinda scummy.


Also, no original deal mentioned, though there likely was one. Else, it makes even less sense to sue now and won't bear any fruit, either.

If you follow the links to the actual lawsuit .pdf it does say that the patent is still in his possession.

Professor Masahiro Iida v. Intel Corporation, 6:22-cv-00662, No. 1 (W.D.Tex. Jun. 24, 2022)

<div class='snippet_line'><em class=''>complaint</em> for patent infringement ( filing fee $ 402 receipt number 0542-16180917), filed by professor masahiro ...

www.docketalarm.com

36. Since October 1, 2014, Professor Iida has been, and is presently, the sole owner of all right, title, and interest in the ’737 patent.

 

[KyaraM]

If you follow the links to the actual lawsuit .pdf it does say that the patent is still in his possession.

Professor Masahiro Iida v. Intel Corporation, 6:22-cv-00662, No. 1 (W.D.Tex. Jun. 24, 2022)

<div class='snippet_line'><em class=''>complaint</em> for patent infringement ( filing fee $ 402 receipt number 0542-16180917), filed by professor masahiro ...

www.docketalarm.com

Then the point still stands. Why only sue literally days before the patent expires, instead of the start of the infringement? Not as if Intel buying another company is a huge secret that only came to light now. It's a pretty dickish move in my book.

 

[InvalidError]

Then the point still stands. Why only sue literally days before the patent expires, instead of the start of the infringement? Not as if Intel buying another company is a huge secret that only came to light now. It's a pretty dickish move in my book.

And if he tries to claim he didn't know about the infringement until now, AMD, Intel, etc. can simply point to their FPGA designers' guides which detail their logic slice/block/whatever in relatively exhaustive details, which would make their use of LUT-6 with a bunch of alternative configuration options one of the worst kept secrets ever.

With only two major FPGA manufacturers and three significant others, it ain't like he can claim there were too many of them out there for him to realistically keep up with the market either.

 

[jhallenworld]

I question whether a year 2000+ ALM patent can be valid because the XC3000 series from the late 80s also had a form of ALM, so should count as prior art: their LUTs had 5 inputs and 2 outputs. Look at figure 6:

XC3000 datasheet

Altera's 8 input / 2 output ALM is just an increase in scale over this.

 

[TerryLaze]

Then the point still stands. Why only sue literally days before the patent expires, instead of the start of the infringement? Not as if Intel buying another company is a huge secret that only came to light now. It's a pretty dickish move in my book.

That's what everybody would do.
They contacted intel in 2018 hoping that they would just give them money without having to go to court, and then they waited till the last possible moment to see if intel would give in.

70. On February 19, 2018, counsel for Professor Iida sent a letter, via certified mail, to the General Counsel of Intel in which she advised him that her firm had become aware that Intel’s PSG “offers FPGAs with adaptive logic modules (ALMs) that appear to be claimed by our client’s US Patent No. 6,812,737 entitled ‘PROGRAMMABLE LOGIC CIRCUIT DEVICE HAVING LOOK UP TABLE ENABLING TO REDUCE IMPLEMENTATION AREA’ (enclosed).” A copy of this letter is attached as Exhibit 5.

 

[Tracymc]

The Claims from his patent ( https://patents.google.com/patent/US6812737 ) are:
What is claimed is:
1. A look up table of M inputs and N outputs, comprising:
a plurality of LUT units; and
an internal configuration control circuit controlling an internal configuration of said plurality of LUT units, wherein said internal configuration control circuit comprises
a plurality of selectors selecting I/O signals of said plurality of LUT units, and
a selector control circuit having a memory, controlling said plurality of selectors in accordance with data stored in said memory, and defining the internal configuration of said plurality of LUT units.
2. The look up table as claimed in claim 1, wherein said plurality of selectors include:
an input signal selector provided at an input of at least one of said LUT units to select an input signal; and
an output signal selector provided at an output of said LUT units selecting an output signal, said input signal selector and said output signal selector being controlled in accordance with the data stored in said memory.
3. The look up table as claimed in claim 1, wherein said plurality of selectors include:
an input signal selector provided at an input of at least one of said LUT units to select an input signal; and
an output signal selector provided at an output of said LUT units selecting an output signal, said input signal selector and said output signal selector being controlled in accordance with the input signal.

1. The look up table as claimed in claim 1, wherein said look up table of M inputs and N outputs is a 6-input 3-output look up table.
2. The look up table as claimed in claim 4, wherein said 6-input 3-output look up table comprises eight 3-input 1-output LUT units.
3. The look up table as claimed in claim 4, wherein said 6-input 3-output look up table comprises four 3-input 2-output LUT units.
4. A programmable logic circuit device comprising: a plurality of logic blocks;

a plurality of routing wires connected to each of said logic blocks;
a plurality of switch circuits provided at an intersection of each of said routing wires;
a plurality of connection blocks provided between an I/O line of each of said logic blocks and each of said routing wires; and
an I/O block performing an input/output operation with external equipment, wherein each of said logic blocks has a look up table of M inputs and N outputs, comprising:
a plurality of LUT units; and
an internal configuration control circuit controlling an internal configuration of said plurality of LUT units, wherein said internal configuration control circuit comprises
a plurality of selectors selecting I/O signals of said plurality of LUT units, and
a selector control circuit having a memory, controlling said plurality of selectors in accordance with data stored in said memory, and defining the internal configuration of said plurality of LUT units.
8. The programmable logic circuit device as claimed in claim 7, wherein said plurality of selectors include:
an input signal selector provided at an input of at least one of said LUT units to select an input signal; and
an output signal selector provided at an output of said LUT units selecting an output signal, said input signal selector and said output signal selector
being controlled in accordance with the data stored in said memory.
9. The programmable logic circuit device as claimed in claim 7, wherein said plurality of selectors include:
an input signal selector provided at an input of at least one of said LUT units to select an input signal; and
an output signal selector provided at an output of said LUT units selecting an output signal, said input signal selector and said output signal selector being controlled in accordance with the input signal.

1. The programmable logic circuit device as claimed in claim 7, wherein said look up table of M inputs and N outputs is a 6-input 3-output look up table.
2. The programmable logic circuit device as claimed in claim 10, wherein said 6-input 3-output look up table comprises eight 3-input 1-output LUT units.
3. The programmable logic circuit device as claimed in claim 10, wherein said 6-input 3-output look up table comprises four 3-input 2-output LUT units.
4. A method of configuring a look up table of M inputs and N outputs, comprising:

providing a plurality of LUT units; and
selectively controlling I/O signals of said plurality of LUT units to set a predetermined mode of an internal configuration.

1. The method of configuring a look up table as claimed in claim 13, wherein the I/O signals of said plurality of LUT units are selectively controlled in accordance with data stored in the corresponding look up table.
2. The method of configuring a look up table as claimed in claim 13, wherein an input signal input to at least one of said LUT units and an output signal output from said LUT unit are selectively controlled in accordance with data stored in the corresponding look up table.
3. The method of configuring a look up table as claimed in claim 13, wherein an input signal input to at least one of said LUT units and an output signal output from said LUT unit are selectively controlled in accordance with a predetermined function of the input signal.

Most of those claims are standard FPGA tools.
I'm pretty sure he has patented the FPGA itself years after it was commercially available.
The first one is amusing. How can you do a LUT without M inputs and N outputs?

I am unclear if you could do an FPGA without them BEFORE he patented it. His understanding of how they worked might have been novel to him, as a newbie in 2001. The question is should this patent ever have been granted in the First place. A patent is a time stamp of what was claimed when, the Patent office does not asses novelty beyond a cursory check by an examiner who is rarely an 'expert in the art'.

Someone who was doing FPGAs in 2000 needs to review this, but as a user not a designer, I don't see anything novel. I'm not an expert so maybe there is something.

 

[InvalidError]

Most of those claims are standard FPGA tools.

More precisely, he patented packaging the common glue logic commonly used to stitch multiple smaller LUTs into different combinations of larger LUTs into his fancy LUTs. The area saving here coming simply from not using global routing and logic resources since they have been added locally to the ALM.

Patents on doing the same obvious things as 5, 10, 20 years ago, just digital, online, more tightly integrated, wireless, etc. as the underlying technology improves suck.