The article said:
LPDDR6 improves this by using four 24-bit sub-channels
Hmmm... I don't see where this number came from. By my reading, they're saying each die has a 24-bit interface that's comprised of two 12-bit subchannels. Because this is LPDDR6 and not regular DDR6, I think there's no DIMM standard to say how many chips you use in parallel. We'll probably get this in some new LPCAMM standard, but I assume that's probably still in the works.
The article said:
DDR5 splits the 64-bit channel used by DDR4 into two independent 32-bit sub-channels
Because we're now talking about
LPDDR6, you should be comparing it to
LPDDR5, which actually used 16-bit subchannels.
The article said:
This makes the standard’s transfer rate much faster than the current DDR5-12054 overclocking record.
LPDDR typically has higher clock speeds than the corresponding DDR standard.
The article said:
It took about a year for DDR5 modules to arrive on the market after it was announced in 2020, and we expect the same with LPDDR6
There are no LPDDR5 SODIMMs, to my knowledge. LPCAMM2, but it came much later.
And speaking of LPDDR5, that standard was released 6 years ago, in Feb 2019.
I'd have liked to see this subject get the proper "Anton" treatment. All I'm getting from this article is a muddled regurgitation of the JEDEC press release.
BTW, the article did link one helpful resource, which is this presentation. It seems to have some rather intriguing details, such as breaking down the subject of the 12-bit subchannel, burst structure & features, and how it maps to CPU cachelines (which are usually 64 bytes).