This is the one in which facts are unequivocal. In 64 bit ISAs RISC-V code is consistently on average 20% or more smaller than x86_64 or arm64.
Anyone can verify this. Download the same version of the same OS e.g. Ubuntu 24.04 (or run them in Docker w qemu emulation, which only takes seconds) and compare the size of various programs that will have the same source code compiled regardless of the ISA e.g. bash, emacs, less ... take your pick. Use the `size` command and look at the TEXT size.
RISC-V is an open source license-free specification. Anyone with the necessary skills and funding is free to implement RISC-V in anything from bit-serial microcontrollers implementing only RV32I (SeRV) to supercomputers. You don't have to ask anyone's permission, or even tell anyone, or pay anyone any money.
If you want to use the RISC-V name and logo commercially and maybe give your input on future directions and ISA extension then you need to join RISC-V International. This is free for individuals and community organisations, $2k/year for startups with fewer than 10 people in their first 2 years, $5k/year for companies with up to 499 employees. What's the salary you're paying for 10 employees? 500 employees?
Or, you can just license the RTL for a ready-made core from an IP company such as SiFive or Andes, the same as you would from Arm. Except they can't make you, you're free to switch to another provider if the quality or features or price don't suit you, and they can't stop you designing your own instead.
You simply can't get into the kind of mess that Qualcomm is finding itself in with the Nuvia acquisition and using the core they designed. We kind of knew that Qualcomm and Apple (etc) can't license their Arm-compatible cores to someone else, but no one (including Q) had any idea that you also could not use someone else's Arm-compatible core by buying the company.
riscv64 and arm64 are so similar technically that you should just assume they are identical in terms of the above, given equal investment and employing equal engineers, at least at the high end.
There is absolutely no reason that someone (probably several someone's) can't make RISC-V cores equal to Apple M1/M2/M3/M4.
There might be a slight difference, but we haven't yet seen the results of ex Apple / AMD / Intel / Qualcomm / Arm engineers building high performance RISC-V cores. Most of those teams started in 2021/2, so will probably have something you can buy in 2026/7/8 or so.
At the low end, RISC-V has a lot of optional extensions that you can leave out if you don't need them, saving silicon area, cost, and energy consumption. Arm doesn't allow subsetting their ISAs. There are some optional things, but the compulsory base is very large -- similar to RISC-V's RVA23 etc profiles that specify a fixed and largish set of extensions for machines running Linux / Android etc.
And there are some things Arm simply doesn't offer, such as a 64 bit version of the Cortex-M0. Arm's 32 bit and 64 bit ISAs are very different (and they've got 3 or 4 32 bit ISAs). RISC-V's are virtually identical other than the different register/address size.
That's SPARC, not RISC-V which is a specific and new ISA. Both are based on RISC principles, but are very different in details.
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