It takes Intel little engineering to put two dies on a CPU because their FSB can be shared between the two dies as easily as it can feed one single die. Intel's engineering work had been done when the current AGTL+ FSB spec was designed, and they can sit back and use it without modification in newer chips. Intel just has to put a little bit of circuitry to facilitate the FSB sharing in the CPU package, make sure that the dies are all wired up and won't exceed a reasonable TDP, and away she goes. This requires the chipset to support FSB sharing, but an MCM sharing a FSB is the same as two CPUs sharing the FSB, and Intel has been doing that ever since the first Pentium SMP setups. FSB sharing support has been included in all Intel desktop chipsets since the 865, excepting the 915 and 925.
AMD would have to do a lot more work as their current on-die memory controller pretty much requires that all cores be on a single die or they would need to make a new socket for two IMCs or slave one die off the other using HTT, which probably would not perform very well. Or they could redesign the CPU to have MCM operation in mind. The Barcelona has two independent 64-bit memory controllers in it. The official word is that the two independent memory controllers are used to allow for synchronous reads and writes, which is not possible with the current 128-bit IMC, and that would improve performance. They are probably right, but it also lets them shut off one IMC so that they can put two dies in a package, each with one IMC working.
So in summary, it would take a CPU redesign due to the IMC and the Barcelona is designed to allow for an MCM. AMD even says they will release the "Shanghai" 8-core MCM chip.