Efficiency is given by the energy used to complete a task.
Read the section titled dynamic power dissipation. TLDR: 2 factors directly change the power consumption, the supply voltage for a transistor and its operating frequency.
Reducing the voltage supply in order to reduce power to the IC introduces a delay, a latency in the speed at which the transistors within the IC can switch.
So, consider the clock is 2t and active on the switch to supply voltage. The transistor output needs to switch to the correct logic level before the next trigger action to be useful, it needs to present its output to the next transistor input or to the IC output within the clock cycle. Designing for this is really complicated.
A low supply voltage reduces the ability of the transistor to do this as the transistor isn’t driven as hard as a transistor at a higher voltage. It takes longer to get to logic 1.
This is known as “slew rate”.
Look it up.
FYI, overclockers increase the supply voltage to their chips to shorten the slew rate time. Driving too hard causes the wave form to “ring”, this causes different problems.
Designers take both these factors into account and work in a neutral area, one that is fast enough and doesn’t overdrive the chip. Slew rate is added to the ring time by the circuit designers to come up with a parameter “settling time”.
Look it up.
Going to Mitch’s example of an IC that does an amount of work at 3GHz with an IPC of 1.2 and a second that performs the same task at 3.6GHz with an IPC of 1. The article shows that everything else being equal the IC that runs at 3GHz will consume less power. It will be more efficient.
Assuming everything performs in a linear manner, increasing the hypothetical 3GHz chip frequency to 3.6GHz the output would be the equivalent of the 3.6GHz chip @4.32GHz
Power consumption increases with frequency, monitor with HWinfo, lock your processor frequency, to for sake of argument 4 GHz in bios. Run cinebench singe thread for 10 minutes and look at HWinfo, CPU power numbers…. Then go back to bios, let the processor run as intended with dynamic boosting… run cinebench single threaded again for 10 minutes while monitoring with HWinfo… look at the power use.
Power consumption increases with voltage, check this with HWinfo, reduce your voltages in bios.. look at the numbers in HWinfo… increase your voltages in bios, rinse and repeat.
The final part, as transistors are pushed toward their limits the source/drain/gate leakages become more problematic, leakages cause heat, they need to be compensated for by increasing voltages.. causing more heat. Leakage is always there to some degree but its effects are problematic as you try to drive a transistor at its limit. As stated earlier, designers try to run their ICs in a neutral region where changes are linear. As you push to the upper limits changes require substantially more power for small frequency gains. Power consumption in this use case is very high… LN2 cooling is your friend at the extremes.