Lenovo Lists Intel Cascade Lake-AP Xeon CPU Lineup

[Guest]

Intel's upcoming Cascade Lake-AP Xeon family of processors consists of 39 different models.

Lenovo Lists Intel Cascade Lake-AP Xeon CPU Lineup : Read more

 

[DavidC1]

It says its a Xeon Platinum 8280M.

It looks like its a Cascade Lake-SP not -AP. Has everyone forgotten about the regular Cascade Lakes already?

 

[Reilly]

but can it run crysis?

 

[bit_user]

Lenovo's listing includes up to 39 different models from the Xeon Bronze, Silver, Gold, and Platinum product lines.

It would've been helpful to see a side-by-side list of equivalent Skylake-SP models. Otherwise, it's hard to see what might've changed.

 

[bit_user]

It says its a Xeon Platinum 8280M.

It looks like its a Cascade Lake-SP not -AP. Has everyone forgotten about the regular Cascade Lakes already?

I guess the article was updated since you posted this, because the article now clearly states these are lists of Cascade Lake-SP models.

 

[redgarl]

The return of the core 2 duo... 2 chips glued together. We are far from Infinity Fabric. It just feels like a desperate attempt.

 

[bit_user]

The return of the core 2 duo... 2 chips glued together. We are far from Infinity Fabric. It just feels like a desperate attempt.

*sigh* this isn't the Cascade Lake-AP. Do you see any > 28-core SKUs in the list?

Also, how do the cross-sectional bandwidth of Cascade Lake-AP and EPYC compare? I betcha don't know, because they haven't said exactly how they're connected (or even how many dies are in there, but 2 is the most reasonable guess). Anyway, UPI didn't exist back in the Core 2 era, so I think it's a baseless comparison.

I think it would be good to focus posts more on facts & information and less on opinion & bashing.

 

[aldaia]

5% extra base clock (wondering about turbo clocks) at the expense of 10% extra TDP.
For instance xeon gold 8160 is 2.10 GHz and 150W vs 8260 2.2 and 165W.
Not sure if datacenters are gonna like it.

 

[jimmysmitty]

The return of the core 2 duo... 2 chips glued together. We are far from Infinity Fabric. It just feels like a desperate attempt.

*sigh* this isn't the Cascade Lake-AP. Do you see any > 28-core SKUs in the list?

Also, how do the cross-sectional bandwidth of Cascade Lake-AP and EPYC compare? I betcha don't know, because they haven't said exactly how they're connected (or even how many dies are in there, but 2 is the most reasonable guess). Anyway, UPI didn't exist back in the Core 2 era, so I think it's a baseless comparison.

I think it would be good to focus posts more on facts & information and less on opinion & bashing.

Don't mind him. He tend to bash Intel and nVidia, yet strangely in his sig has a nVidia product.

That said it would most likely be UPI connecting the two dies together much like it connects sockets. That's the only way I could see them doing it and it working well.

With Core 2 it was never an issue though. On chip the dies communicated fast enough. Their biggest weakness was memory since it still lacked an IMC. For the desktop that didn't matter but server was an issue, especially higher end servers.

 

[bit_user]

The return of the core 2 duo... 2 chips glued together. We are far from Infinity Fabric. It just feels like a desperate attempt.

*sigh* this isn't the Cascade Lake-AP. Do you see any > 28-core SKUs in the list?

Also, how do the cross-sectional bandwidth of Cascade Lake-AP and EPYC compare? I betcha don't know, because they haven't said exactly how they're connected (or even how many dies are in there, but 2 is the most reasonable guess). Anyway, UPI didn't exist back in the Core 2 era, so I think it's a baseless comparison.

I think it would be good to focus posts more on facts & information and less on opinion & bashing.

Don't mind him. He tend to bash Intel and nVidia, yet strangely in his sig has a nVidia product.

I'm pretty sure it's a "her", not that it matters. I read the username as "red girl", and the profile pic is of a well-known red-haired female anime character from behind.

https://en.wikipedia.org/wiki/Asuka_Langley_Soryu

That said it would most likely be UPI connecting the two dies together much like it connects sockets. That's the only way I could see them doing it and it working well.

Sure, but they haven't revealed the topology, clock speed, or the number of links connecting them.

I think it would be interesting if they wired only one link in-package, and brought out the other 4. Then, the systems vendor could decide how to route the other pairs. Perhaps, in a 1-socket system, they will route however many pairs reach the socket so that all three links connect the two dies.