Libre-SOC developers sent the first test ASIC to TSMC's manufacturing facilities.
Libre-SOC Releases First Non-IBM OpenPOWER Chip in Decade : Read more
Libre-SOC Releases First Non-IBM OpenPOWER Chip in Decade : Read more
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I wish it was on GloFlo 12nm instead of TSMC 180nm.
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Did you even read the article? The architecture is only 130k logical gates in size, let's just assume 5(I know, I know not all logic gates requires that much transistor or uses that few transistor and that there are resistors etc but let's just assume 5 transistor) transistors per logic gate, 130k x 5 = 650k transistors. GloFo 12nm has a transistor density of 36Million Transistors in a single mm2, 650k Transistor is only ~2% of 36Million, so the 650k design would only use 2% of a millimeter, smaller than a speck of dust I have no idea how are you going to route and connect dozens to hundreds of BGA traces through something the size of a speck of dust. 😑I wish it was on GloFlo 12nm instead of TSMC 180nm.
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