LoongArch to power next-generation Loongson CPUs.
Loongson Technology Develops Its Own CPU Instruction Set Architecture : Read more
Loongson Technology Develops Its Own CPU Instruction Set Architecture : Read more
However, only time will tell whether the company can actually develop a competitive ecosystem for its LoongArch.
It's probably based on some existing ISA anyway and claiming it's some "brand new tech that will put the West to shame"Using RISC-V would be a nice move.
Inventing their own ISA is only going to waste software development efforts.
Putting together your own ISA is easy enough, the really tedious part is figuring out what instructions are most useful and performance-critical, most of which achievable by profiling software on existing architectures. The rest is mainly a matter of coming up with your own names, an efficient operation encoding scheme and operand packing formats, then plugging all of that into a cross-compiler such as a customized GCC to spit out native binaries.And we're supposed to believe that, why?
Putting together your own ISA is easy enough, the really tedious part is figuring out what instructions are most useful and performance-critical, most of which achievable by profiling software on existing architectures. The rest is mainly a matter of coming up with your own names, an efficient operation encoding scheme and operand packing formats, then plugging all of that into a cross-compiler such as a customized GCC to spit out native binaries.
An ISA is just the instruction set with supporting architectural features such as the registers and flags instructions can access, it isn't tied to any particular implementation in software emulators, re-compilers, FPGA implementations, silicon, etc. Anyone can write a minimalist one on a napkin if they wanted to, that isn't the hard part.
There is no 'in this context' here, an ISA is just a set of definitions by definition. If China wants to rip off the open-source MIPS ISA and spare itself the trouble of writing their own together from scratch, more power to them.You just spewed a bunch of garbage, you clearly don't know what an ISA is in this context.
From what I am reading, i think Titan's understanding of the ISA is actually accurate. Considering that the x86 and x64 along with the RISC achitectures are essentally the same thing just with different register access and optimised coding for the CISC.You just spewed a bunch of garbage, you clearly don't know what an ISA is in this context.
Meanwhile "LoongArch" is turning out to be a modified MIPS64 ISA where they've merely renamed some of the instructions.
https://www.realworldtech.com/forum/?threadid=201588&curpostid=201593
By: Ariadne Conill (ariadne.delete@this.dereferenced.org), April 16, 2021 10:53 pm
"
I did some digging into this, as I maintain the MIPS64 port in Alpine, and was planning to target Loongson at some point.
From what I can tell, LoongArch is just a fork of the MIPS ISA, in a similar way to how MIPS32r5 and MIPS64r6 are backward-incompatible forks of the MIPS ISA. I conclude this based on the fact that LoongArch offers the same extensions that MIPS CPUs do, just with slightly different names, as can be seen in this translated press release. For example, what MIPS CPUs call the Virtualization Extension (VZ), LoongArch calls the LoongArch Virtualization Extension (LVZ). Another example is that the MIPS SIMD instructions (MSA) are renamed to LoongArch Vector Extension (LSX).
Specifically, I believe LoongArch to be a fork of MIPS64r6. "
InvalidError's position on the ISA is correct: it's trivial to create new ISA. But why almost no one does that? Because ISA without software for it is completely useless.
It looks like they want to maintain some compatibility with MIPS with more extensibility:
So nothing outstanding from technical standpoint: not a breakthrough but also not a reinventing the wheel.
Security through obscurity will only get you so far. I mean for kicks, imagine if China did make a new ISA, but required a security clearance to even work with it.It is a shame really, Making a new ISA would be an excellent idea to reduce the ability of hackers
Most modern processors take the best of both worlds in implementation. The only thing at this point that we could improve is trying to find ways to make software as linear as possible. But if you get that far and you have a large set of data points, we have a better option to run it on: a GPU.and also reduce calls and latency. If an new internal registry system were to be built, an optimised ISA could be a game changer for Speed and process. It is the Whole idea of the advantages of CISC over RISC so why not.
Yes and no. Everything above the kernel level space is likely abstracted enough that you can compile it for a different target and be fine. It's everything at the kernel level that can't simply be compiled for another target as-is. Especially if it's poking at quirks of the ISA or in some cases, system requirements. For example, you can't load a bog standard amd64 build of Linux onto a PS4 despite the PS4 having an x64 processor. Why? Because the amd64 build of Linux still adheres to the IBM PC standard and expects things that the PS4 doesn't have because the PS4 wasn't designed to be IBM PC compliant.Its something I dont understand. To get old programs to work on different platforms, you just force the source code through a compiler dedicated to the Chip and the ISA it understands. So getting Windows 10 to work on ARM is as simple as optimising the code through an ARM compiler. The only drawback is the speed at wheich it runs.
The biggest bottleneck to most CPUs today is conditional jumps, not the hardware architecture or instruction set. There is very little that the ISA can do about typical software having conditional branches every 10-20 instructions, that's why CPUs focused on single-thread performance have ridiculously deep out-of-order superscalar speculative execution to brute-force their way through code.an optimised ISA could be a game changer for Speed and process.
Conditional jumps through IF or FOR statements would easily benefit from direct access to a new Jump register. The Line being read and loaded up to the ISA hardware can automatically do the searches for the new jump address while the comparison is being made, so that the Jump address is ready or almost ready by the time that the comparison in the conditional jump is made. Accessing that new jump space, file or Class would then be quickly accessed using matricies codes to access the RAM or Diskspace required. The simple fact is that the 8086 IBM ISA dealt with a simple varied set of instructions that allowed the user to do anything they wanted to if they could figure out the coding for it. The General purpose registers were developed because of coding like Bubblesort that would need temp stores that could allow quicker access, but still had to have user control to directly load Data onto the registers. A new ISA can figuratively be slightly more complex, in that an IF command automatically loads the operands into new General purpose registers (reducing the mov instructions and making conditional statements less intense by parralleling the work load directly. As most games with user control are mostly controlled by conditional commands, changes like this to the instruction and ISA would not require code change at all.The biggest bottleneck to most CPUs today is conditional jumps, not the hardware architecture or instruction set. There is very little that the ISA can do about typical software having conditional branches every 10-20 instructions, that's why CPUs focused on single-thread performance have ridiculously deep out-of-order superscalar speculative execution to brute-force their way through code.
Making software faster is mostly in software developers' court, got to reduce the amount of speculative branches and make those that cannot be eliminated more predictable. There isn't a whole lot more that hardware can do besides brute-force harder by adding more of everything.
Looks like you have very little idea of how modern CPUs work.Conditional jumps through IF or FOR statements would easily benefit from direct access to a new Jump register. The Line being read and loaded up to the ISA hardware can automatically do the searches for the new jump address while the comparison is being made, so that the Jump address is ready or almost ready by the time that the comparison in the conditional jump is made.
Looks like you have very little idea of how modern CPUs work.
Speculative execution is when a CPU guesses which branch will be (not) taken, executes based on that assumption and discards the work that it did on speculation if it the guess turned out to be wrong. Modern CPUs can be 200+ instructions deep into speculative branches. Your "jump address register" is unnecessary since the jump address is already encoded in the jump instruction itself.
Out-of-order execution is when a CPU looks ahead of the current instruction pointer or speculative branch (up to 352 instructions ahead for Intel's Sunny Cove) to figure out the most effective execution order based on instruction dependencies and latencies, then re-arrange them to maximize execution resources usage. That's how modern CPUs can still manage to average 3+ instructions per clock despite branches. It also means 200+ instructions at various stages of execution potentially getting thrown out when a prediction is wrong.
The problem with jumps is that prediction will never be 100% reliable and to fill that 200+ instructions deep re-order buffer, the CPU will end up 10+ layers deep into predictions.
You should go read some architectural overviews of ARM CPU architectures. The main reason ARM CPUs are getting faster is because the core designs are picking up more of those same pipelining, out-of-order, superscalar, speculative, etc. tricks. Also, Intel did not invent most of those tricks, it got them from DEC which came up with them ~30 years ago for its Alpha CPUs. Since true RISC CPUs need more instructions to perform the same work, DEC needed those tricks long ahead of its time to get a competitive advantage.This isnt about pedictive coding, its about ISA and the advantages of Possible change to a relative old acchitecture from IBM that is 50 years+ old.
IBM did not create x86, it was just Intel's first major client for x86. x86 isn't 50+ years old either since Intel's 8086, the 16bits chip after which the instruction set is named, was launched in 1978, 43 years ago.This isnt about pedictive coding, its about ISA and the advantages of Possible change to a relative old acchitecture from IBM that is 50 years+ old.
You should go read some architectural overviews of ARM CPU architectures. The main reason ARM CPUs are getting faster is because the core designs are picking up more of those same pipelining, out-of-order, superscalar, speculative, etc. tricks. Also, Intel did not invent most of those tricks, it got them from DEC which came up with them ~30 years ago for its Alpha CPUs. Since true RISC CPUs need more instructions to perform the same work, DEC needed those tricks long ahead of its time to get a competitive advantage.
IBM did not create x86, it was just Intel's first major client for x86. x86 isn't 50+ years old either since Intel's 8086, the 16bits chip after which the instruction set is named, was launched in 1978, 43 years ago.
You should go read some architectural overviews of ARM CPU architectures. The main reason ARM CPUs are getting faster is because the core designs are picking up more of those same pipelining, out-of-order, superscalar, speculative, etc. tricks. Also, Intel did not invent most of those tricks, it got them from DEC which came up with them ~30 years ago for its Alpha CPUs. Since true RISC CPUs need more instructions to perform the same work, DEC needed those tricks long ahead of its time to get a competitive advantage.
Hm, no. That has absolutely nothing to do with pipelining. Go (re-)take compsci 101.Pipelining is useful when watching Video online for example
I wanted to poke at something real quick, but I'll probably stop responding afterwards.The Fact that the M1 RISC chips that avoid complex ISA and Large pipelines are now proving that they can possibly beat and excell CISC is also another Proof that CISC and Pipelining is a wasteful and deliciously poor decision to make.
Hm, no. That has absolutely nothing to do with pipelining. Go (re-)take compsci 101.
I wanted to poke at something real quick, but I'll probably stop responding afterwards.
I really don't see any advantage or disadvantage between ARM and x86 and as I've parroted around before, the ISA in modern CPU design is largely irrelevant. What matters is how you implement the CPU. If the ISA is the only thing that matters, then even MediaTek's ARM SoCs should smoke the living heck out of Intel's CPUs clock for clock.
- Although it hasn't gotten into any real detail as of late, the number of pipeline stages on Apple's SoC's has been estimated to be 12 for the A6 (https://www.anandtech.com/show/6330/the-iphone-5-review/8) and 16 for the A9 (https://en.wikipedia.org/wiki/Apple_A9). According to Wikichip, Kaby Lake has 14-19 stages (https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake).
- The core difference between a RISC and CISC system now and days is simply the addressing modes avaialble in the opcodes. RISC can only do data modification using registers or immediate values. CISC (or at least x86) allows for data modification using memory locations. However, internally a CISC instruction using memory locations can easily be translated to a series of load/store instructions in RISC and the CPU does the same amount of work anyway.
- Of note, ARM has a variable length instruction set, the THUMB-2 instruction set, for precisely the same reason why CISC has a variable length instruction set: code density.
- Also in order to be ARMv8 compatible, the CPU has to support AArch64, ARM32, and THUMB-2. (https://armkeil.blob.core.windows.n...d-multimedia/ARMv8_InstructionSetOverview.pdf)
Exactly. Once x86 adopted instuction decoders that output RISC-like micro-OPs to simplify the rest of the execution pipeline, RISC and CISC became effectively indistinguishable. Even RISC CPUs use micro-OPs to handle instructions that don't have an 1:1 relationship with execution resources.I really don't see any advantage or disadvantage between ARM and x86