News Loongson Technology Develops Its Own CPU Instruction Set Architecture

[ginthegit]

Exactly. Once x86 adopted instuction decoders that output RISC-like micro-OPs to simplify the rest of the execution pipeline, RISC and CISC became effectively indistinguishable. Even RISC CPUs use micro-OPs to handle instructions that don't have an 1:1 relationship with execution resources.

So you are conceeding that you actually dont understand Pipelining and you just got owned.

And this is exactly tthe point I made and you mocked.

a 1:1 relationship is obvious considering that the CPU core is always the fastest component on the System and that everthing must sychronise to it. At least that is how the old IBM compatable systems used to do it via the BIOS. Now that Kernels have taken over everthing, the OS adds more overhead to the execution of Hardware due to its Scheduler. The only exceptions to this is when the CPU has Hirect hardwired connections rather than through Matherboard controller chips.

And again you are over simplifying the ISA to Execution of commands and the cycles that it moves through (see the link above explaining pipelines). The ISA is purly the Instructions that are avalable for direct decode like MOV , ADD , SUB , IF , FOR etc and how they are coded with the rest of the operand. RISC and CISC are still very different here, as CISC adds extra operands including things like the Math Co-processor, that RISC has to operate using address codes and sending the data in a more traditional sense of instruction by instruction. CISC uses a process like a C FUNCTION that one command with its data attached can be sent to a hardware decoder that will push the data through said hardware and will come out with a result without all the independant commands, as these are hardwaired into this dedicated ISA decoder.
Wikipedia will explain the commands of the ISA, but I find that the explanation of CISC and RISC in how they execute data is very Macro and high level, simply on the fact that they dont understand Logic gates and State logic construction for sequential logic (including dedicated Next state logic). There are very few of us that can construct logic cores from Next state logic, Boolean algebra and shift registers.

And Again, I will make my point, the RISC command set (and CISC base set of instructions) can be seriously updated and stream lined, but Industrial standardisation is more prominent that innovation, and it would mean New compilers and maybe re-working the Kernel format (to a smaller and more Matricies based constructs). Which was my point since the beginning!

 

[InvalidError]

The ISA is purly the Instructions that are avalable for direct decode

No, an ISA is the entire set of supported instructions and their relationships, regardless of whether they are direct decodes or require micro-OPs.