News Materials Breakthroughs Paves Path to 2D Transistors

[Admin]

Multinational team of researchers reckon they have removed the three major barriers to the commercial production of 2D materials, allowing physicists' 2D transistor dreams to become reality.

Materials Breakthroughs Paves Path to 2D Transistors : Read more

 

[hotaru251]

someone call Jensen...he might want to get a diaper ready when moores law isnt "ended" as he claims as excuse to keep GPU prices increasing.

 

[Eximo]

Well, give it ten to twenty years when production scaling is achieved...

If you think a CPU with two or three layers of stacking is expensive, wait until you have hundreds of layers.

 

[helper800]

Just wait until we have the materials science to increase the efficiency of power transfer. All the cooling we currently need for all electronics is because of the small amount of resistance to the transfer of power. When we either create or find a way to reduce this resistance, without exotic means, we could essentially put as much power as we want into any part with very little cooling required. Imagine how small our electronics could be if cooling systems only needed to be 1/10th the size they are now.

 

[TJ Hooker]

Just wait until we have the materials science to increase the efficiency of power transfer. All the cooling we currently need for all electronics is because of the small amount of resistance to the transfer of power. When we either create or find a way to reduce this resistance, without exotic means, we could essentially put as much power as we want into any part with very little cooling required. Imagine how small our electronics could be if cooling systems only needed to be 1/10th the size they are now.

What "transfer of power" are you referring to?

 

[Eximo]

Likely speaking of room temperature superconductors and the like. Not likely to happen anytime soon. Power requirements will go down in 2D materials simply because there is less mass doing the logic.

There have been efforts to integrate cooling solutions into silicon and die stacks, even delivering power via liquid coolant. That hasn't really made it that far.

 

[helper800]

What "transfer of power" are you referring to?

From the PSU through circuitry and board components to CPU and other major parts.

 

[helper800]

Likely speaking of room temperature superconductors and the like. Not likely to happen anytime soon. Power requirements will go down in 2D materials simply because there is less mass doing the logic.

There have been efforts to integrate cooling solutions into silicon and die stacks, even delivering power via liquid coolant. That hasn't really made it that far.

The the amount of power lost as heat to components and everything in-between is what I am talking about. If we can reduce this to less than a few percent, it would revolutionize electronics.

 

[TJ Hooker]

From the PSU through circuitry and board components to CPU and other major parts.

Most of the power is consumed (i.e. converted to heat) by the chips themselves. Not as losses between the chips and the power source. Even if you eliminated all losses between the PSU and the actual silicon dies, it wouldn't make a big difference in cooling requirements, because most (active) cooling is already basically just for the heat given off by the dies themselves. I guess you could get rid of VRM heatsinks though.

 

[helper800]

Most of the power is consumed (i.e. converted to heat) by the chips themselves. Not as losses between the chips and the power source. Even if you eliminated all losses between the PSU and the actual silicon dies, it wouldn't make a big difference in cooling requirements, because most (active) cooling is already basically just for the heat given off by the dies themselves. I guess you could get rid of VRM heatsinks though.

The power lost as heat no matter where it occurs is due to materials inefficiency. All power lost as heat is due to resistance.

 

[bit_user]

The power lost as heat no matter where it occurs is due to materials inefficiency. All power lost as heat is due to resistance.

As long as semiconductors are capable of reducing entropy, they'll be consuming energy.

Do you have any figures on how much power is lost through distribution (i.e. copper traces) vs. transistors and other components?

 

[helper800]

As long as semiconductors are capable of reducing entropy, they'll be consuming energy.

Do you have any figures on how much power is lost through distribution (i.e. copper traces) vs. transistors and other components?

Entropy is very insignificant on the scale we are talking about, but is something I certainly missed.

It has been a while but I believe it goes something like this: Power loss = Current squared x resistance. The formula for power is: Power = Voltage x Current. Given these formulas if you reduce current by the same amount that you increase voltage you will exponentially reduce the power lost as heat. For example if you increase voltage by a factor of 10 and decrease current by a factor of 10 you will reduce the amount of heat lost by 100 times. The amount of power lost due to heat depends on many factors like gage of the wire/trace, length of the wire/trace, and the properties of the materials used for that wire/trace because these things all affect resistance.

 

[bit_user]

If you think a CPU with two or three layers of stacking is expensive, wait until you have hundreds of layers.

Don't confuse layers within a die with die-stacking. Very different things. I believe modern chips, like mainstream CPUs and phone SoCs, already have dozens of layers, even with no stacking.

 

[Eximo]

Don't confuse layers within a die with die-stacking. Very different things. I believe modern chips, like mainstream CPUs and phone SoCs, already have dozens of layers, even with no stacking.

True enough, but a 2D material would allow for MANY more layers. Either there will be a lot of redundancy in the designs or there will be a lot of unit testing and binning before final assembly.

Or they will make many logic layers, test them, and then stack them. Test again, and so on until they have the desired product. A lot of options.

Could be 2D die, cooling and power layer, 2D die, cooling and power layer and so on.

 

[bit_user]

True enough, but a 2D material would allow for MANY more layers.

Well, what they didn't say was how the areal density of these new transistors would compare to the current state-of-the-art. Without knowing that, we can't say whether or not you could only achieve comparable density through more layers.

What I'd be worried about is that you need a really flat surface on which to grow these 2D transistors. The more layers you have, the more likely it seems you'd end up with lumps. So, I wonder if it's not already self-limiting.

Anyway, I think modern chips have transistors on more than one layer, so I don't necessarily see it as either/or.

Or they will make many logic layers, test them, and then stack them. Test again, and so on until they have the desired product.

I think you don't want thick stacks of logic. But DRAM and NAND have been getting stacked for a while.

Could be 2D die, cooling and power layer, 2D die, cooling and power layer and so on.

I think there are way too many interactions between those layers for stacking to be a viable alternative to the conventional layer sandwich. Stacking has overheads, if you'll excuse the pun.

 

[Eximo]

I think you don't want thick stacks of logic. But DRAM and NAND have been getting stacked for a while.

I think there are way too many interactions between those layers for stacking to be a viable alternative to the conventional layer sandwich. Stacking has overheads, if you'll excuse the pun.

Silicon atoms about about .132 nm, and any design logic is probably going to need 2 or 3, so we are looking at 1nm actual size as the lower limit for silicon. 2D materials might cut that in half, but that would still have a limit we would reach very soon. And I don't think they are talking about making A4 letterhead size chips. At some point they will have to be stacked to keep progressing forward and utilize existing packaging techniques. Not to mention stability and ergonomics.

As to the flat surfaces, that is what electron microscopes are for. You just shave layers off a block of silicon until it is flat enough for their confined growth technique (which I'm sure they did). They are more or less talking about self assembling circuitry via selective crystal growth as a means to mass produce 2d materials to a specification. That material's interface to the outside world is likely to rely on lithography and more typical silicon substrates and techniques.

I get what you are saying about putting the layers too close together, but the whole idea might be that said layers could be part of the logic too. Laying out a regular grid of P and N type materials is one thing, getting them to do something might mean connecting them from top or bottom, or likely both.

If you look at CMOS sensors or HBM or AMD's 3DVcache it is pretty crazy layered stacking already. And some of that is lithography to burn out trenches and things and the deposition layers with doping chemicals, and the actual surface polishing to remove back down to the original layer, and repeats to build out silicon vias. Pretty crazy.

I don't see anything wrong with applying the same thing to a 2D layer.

 

[bit_user]

If you look at CMOS sensors or HBM or AMD's 3DVcache it is pretty crazy layered stacking already. And some of that is lithography to burn out trenches and things and the deposition layers with doping chemicals, and the actual surface polishing to remove back down to the original layer, and repeats to build out silicon vias. Pretty crazy.

I'm sure the cross-sectional bandwidth within a silicon die is at least 10x what they get between adjacent dies in a stack.

Stacking is great for DRAM or even cache. Maybe it'll turn out to be good for stacking distinct cores atop each other. However, I don't expect to see a single core split between layers.