Gon Freecss :
I hate to sound like a wingnut but maybe all these delays with 10mn are being exaggerated to buy some time for their teams to regroup and figure out a tenable redesign.
Intel isn't going to can its medium term product roadmap because of some performance penalties.
I have to agree with randomizer on this one. Intel has already spent time in money on designs for the next 3 generations. Cannon Lake is a port of Skylake to 10nm. Die shrinks provide lower power consumption and better performance using the same architecture. Intel has leveraged a process lead over AMD for ~20 years to help create and maintain a performance gap. They would not willingly give up this advantage, because it is giving away revenue to AMD.
https://en.wikipedia.org/wiki/Die_shrinkIntel, in particular, formerly focused on leveraging die shrinks to improve product performance at a regular cadence through its Tick-Tock model. In this business model, every new microarchitecture (tick) is followed by a die shrink (tock) to improve performance with the same microarchitecture.
And you're grossly wrong about Intel maintaining its performance lead mainly thanks to the process. It's the architecture first and foremost, then the process.
What I stated it completely accurate, and not "Again, wrong." The history of the architecture is proof of the facts not counting the wiki reference. While there might be minor architectural changes/improvements, which involve different IP at smaller nodes, the whole of the architecture was not redesigned!
Your words not mine!And you're grossly wrong about Intel maintaining its performance lead mainly thanks to the process.
My exact words!Intel has leveraged a process lead over AMD for ~20 years to help create and maintain a performance gap.
This has become off topic, and this will be my last response on the subject.