Milestones in CPU development?

[dan3141592653]

Hi all.

I am writing a paper that is outlining the key developments and achievements in CPU history.

I have talked about;
Transistors
L1 cache
Superscalar architecture
L2 cache
MMX/3dnow instruction sets
I want to talk about SSE but I dont fully understand what it is
Fist 64bit Intel itanium
Branch predication, speculative execution
L3 cache
Dual core
Hyperthreading
Turboboost

Please let me know if in your opinion I am missing anything worth talking about. I want to talk about technologies used from the 4004 in 1971 all the way to today.

Thanks people

 

[jitpublisher]

The first one that comes to mind is the contrast to Superscalar, Super Pipelining. Perhaps you have included that discussion as a subset already.

 

[dan3141592653]

The first one that comes to mind is the contrast to Superscalar, Super Pipelining. Perhaps you have included that discussion as a subset already.

No I haven't yet, good idea. Thank You

 

[martinch]

Might be worth covering hardware-accelerated common functions, e.g. crypto (AES acceleration), video (Intel QuickSync, etc), etc, mainstream 8/16/32/64-bit x86 and multi-core CPUs, incorporation of co-processors (I remember separate maths co-processors), integrated memory controllers, moving to SoC-style architecture, hardware visualisation support, instruction/data segregation (No-X bit) ... tbh, you can probably just step through the Wikipedia articles on the CPU architectures from 1995-2012, and pick up the new features. It's probably also worth contrasting against the first computers (Z1-Z3, ENIAC, etc - especially the Z-series, as IIRC they're close to modern CPUs in design principles).

I want to talk about SSE but I dont fully understand what it is

IIRC, it's basically SIMD instructions

 

[dan3141592653]

Might be worth covering hardware-accelerated common functions, e.g. crypto (AES acceleration), video (Intel QuickSync, etc), etc, mainstream 8/16/32/64-bit x86 and multi-core CPUs, incorporation of co-processors (I remember separate maths co-processors), integrated memory controllers, moving to SoC-style architecture, hardware visualisation support, instruction/data segregation (No-X bit) ... tbh, you can probably just step through the Wikipedia articles on the CPU architectures from 1995-2012, and pick up the new features. It's probably also worth contrasting against the first computers (Z1-Z3, ENIAC, etc - especially the Z-series, as IIRC they're close to modern CPUs in design principles).

I want to talk about SSE but I dont fully understand what it is

IIRC, it's basically SIMD instructions

Great post, lots of food for thought. Thank You.

Would you say MMX was the first popular instance of SIMD and SSE built of that by adding support for floating point numbers

 

[martinch]

Great post, lots of food for thought. Thank You.

No prob

Would you say MMX was the first popular instance of SIMD and SSE built of that by adding support for floating point numbers

It depends what you mean by "popular". SIMD essentially originated in super-computers (because SIMD is useful for vectors, which is useful for scientific calculation), and the first real "mainstream" appearance was in the Sun UltraSPARCs, which was marginally ahead of Intel (via MMX). Apparently (I had to look it up - its been a while since I looked at CPU architecture), MMX re-used the floating-point registers, so only worked on integers, whereas SSE incorporated more instructions and worked on floating-point, so yes. Apparently 3DNow also worked on floating-point data. I would also note that both Intel and AMD's developments around this time were important (circa. 1995-2005 AMD were innovative, introducing the first true dual-core CPU, and the 64-bit extensions to the x86 architecture *insert shudder at the thought of IA64 being mainstream*)

 

[jitpublisher]

AMD's pioneering of the 64 bit extensions and the first dual core processor gave Intel reason to get off its butt and do something besides releasing a new processor every 3 months and simply up the processor speed by 100 mhz, and charge a premium for it.

 

[dan3141592653]

Great post, lots of food for thought. Thank You.

No prob

Would you say MMX was the first popular instance of SIMD and SSE built of that by adding support for floating point numbers

It depends what you mean by "popular". SIMD essentially originated in super-computers (because SIMD is useful for vectors, which is useful for scientific calculation), and the first real "mainstream" appearance was in the Sun UltraSPARCs, which was marginally ahead of Intel (via MMX). Apparently (I had to look it up - its been a while since I looked at CPU architecture), MMX re-used the floating-point registers, so only worked on integers, whereas SSE incorporated more instructions and worked on floating-point, so yes. Apparently 3DNow also worked on floating-point data. I would also note that both Intel and AMD's developments around this time were important (circa. 1995-2005 AMD were innovative, introducing the first true dual-core CPU, and the 64-bit extensions to the x86 architecture *insert shudder at the thought of IA64 being mainstream*)

Hi, thanks for your input. I am a bit confused at what was the first 64bit.

Some of my research is telling me intel itanium was the first 64 bit, but id didn't run on x86?. The AMD was more successful due to it being x86 compatible? Did the AMD have any development firsts over the itanium?

 

[dan3141592653]

Great post, lots of food for thought. Thank You.

No prob

Would you say MMX was the first popular instance of SIMD and SSE built of that by adding support for floating point numbers

It depends what you mean by "popular". SIMD essentially originated in super-computers (because SIMD is useful for vectors, which is useful for scientific calculation), and the first real "mainstream" appearance was in the Sun UltraSPARCs, which was marginally ahead of Intel (via MMX). Apparently (I had to look it up - its been a while since I looked at CPU architecture), MMX re-used the floating-point registers, so only worked on integers, whereas SSE incorporated more instructions and worked on floating-point, so yes. Apparently 3DNow also worked on floating-point data. I would also note that both Intel and AMD's developments around this time were important (circa. 1995-2005 AMD were innovative, introducing the first true dual-core CPU, and the 64-bit extensions to the x86 architecture *insert shudder at the thought of IA64 being mainstream*)

Thanks again, good man.

 

[martinch]

One other thing that's probably worth looking at - RISC vs CISC design principles and the implications of each for compilers.

Some of my research is telling me intel itanium was the first 64 bit, but id didn't run on x86?.

It's a different architecture, known as IA64, which is a completely different instruction set to x86. My memory is a little fuzzy on this, but I seem to remember it having a very slow x86 emulation mode (as in an order of magnitude slower), so effectively every piece of software would need to be recompiled for it, which is kinda bad for backwards compatibility, and would be hugely aggrevating for "normal" users (i.e. not enterprise).

The AMD was more successful due to it being x86 compatible?

AMD's x86-64 is what's used now by current Intel/AMD CPUs. The instruction set is an extension of the existing 32-bit x86 instruction set, so x86-64 processors can run 32-bit x86 code without issue (i.e. way better backwards compatibility).

 

[KingDingDong]

The death of Moore's Law.

 

[dan3141592653]

The death of Moore's Law.

Good idea, thanks

Why is moores law levelling off? I was thinking about using this in conclusion, and talk about quantum computing briefly

 

[KingDingDong]

The cynical view is because there is no pressure from AMD and Intel is getting fat and lazy. I am sure there is a more technical reason as well but talk of billions of transistors makes my brain hurt.

 

[dan3141592653]

Whats the difference between a CPU instruction and an extension. I understand that an instruction set is physically hardware/paths within the CPU, are extensions the same?

 

[dan3141592653]

*insert shudder at the thought of IA64 being mainstream*)

Haha I have just been researching iAPX 432 and I nearly know what you mean

 

[martinch]

Whats the difference between a CPU instruction and an extension.

By stating that the x86-64 instruction set is an extension of the 32-bit x86 instruction set, I simply meant that it was a superset of the 32-bit instruction set - i.e. it contained all of the 32-bit instructions, plus extra 64-bit instructions.

 

[martinch]

I am sure there is a more technical reason as well but talk of billions of transistors makes my brain hurt.

It's kinda hard to make large transistor count/area wafers with high yield (look at the GPUs), and modern CPUs are largely fast enough, so focussing on performance-per-watt may well be a reasonable approach. One of my colleagues is ex-Intel, and they were saying that the chip guys were having "fun" hitting 3GHz due to them experiencing quantum effects (obviously, this was a while ago when they were there).

 

[hang-the-9]

You should include some of the ULV CPUs also since that is what is driving the mobile market which is huge and is a big growth area. CPUs in smartphones/tablets. ARM and those types of chips. Without the low power and small size you won't have all of those bajillion iPhones around. Those are as big any huge jumps on CPU advancements.

Don't forget the Digital Alpha chips that for a short time where very advanced compared to Intel and AMD, just did not have a market. https://en.wikipedia.org/wiki/DEC_Alpha

 

[fport]

Are you examining just Intel and Amd? There was Motorola with its big endian approach like IBM's RISC chips.
ASIC's, SOC coming from concepts like VLSI development and increasing sophistication. Is IPC driving development
as the speed curve flattens. Why ARM or Snapdragon?

 

[dan3141592653]

You guys are legends, now I have to squeeze all theese ideas in, I only got 6 sides a4 :S

 

[fport]

There's always the appendices and footnotes and illustrations and url's. ))

Software being frozen into hardware. Software choices making hardware that conforms
to and speeds it up. Remember LISP machines..... or I never met a cache I didn't like?

 

[dan3141592653]

There's always the appendices and footnotes and illustrations and url's. ))

Software being frozen into hardware. Software choices making hardware that conforms
to and speeds it up. Remember LISP machines..... or I never met a cache I didn't like?

I dont think im going to reference anything. I have been learning the concepts and writing my description of them. I used a plagiarism checker and got a 100% pass.

I talked alot about cache. Pentium pro being first on die L2 and I talked about the corei3/i5/i7 series being first on die L3 was I right?

 

[fport]

https://people.apache.org/~xli/presentations/history_Intel_CPU.pdf

Intel Pentium 4, 2000
L3 cache in extreme edition.

https://en.wikipedia.org/wiki/Pentium_4

In September 2003, at the Intel Developer Forum, the Pentium 4 Extreme Edition (P4EE) was announced,
just over a week before the launch of Athlon 64 and Athlon 64 FX. The design was mostly identical to
Pentium 4 (to the extent that it would run in the same motherboards), but differed by an added 2 MB of
level 3 cache. It shared the same Gallatin core as the Xeon MP, though in a Socket 478 form factor
(as opposed to Socket 603 for the Xeon MP) and with an 800 MT/s bus, twice as fast as that of the Xeon MP.

http://www.quepublishing.com/articles/article.aspx?p=481859&seqNum=19

Pentium 4 Extreme Edition
In November 2003, Intel introduced the Extreme Edition of the Pentium 4, which is notable for being
the first desktop PC processor to incorporate L3 cache. The Extreme Edition (or Pentium 4EE) is
basically a revamped version of the Prestonia core Xeon workstation/server processor, which has
used L3 cache since November 2002. The Pentium 4EE has 512KB of L2 cache and 2MB of L3 cache,
which increases the transistor count to 178 million transistors and makes the die significantly larger
than the standard Pentium 4. Because of the large die based on the 130-nanometer process, this chip
is expensive to produce and the extremely high selling price reflects that.

Dunno really - had an Amiga back then.