Although we didn't count the contacts, we can assume that each section holds 859 contacts.
It shouldn't take more than a couple minutes to count them. Going by that picture, each half contains a grid of 79 rows of 10 pads, plus two shorter columns near the edge containing another 69, so (790 + 69) x 2 = 1718.
What we don't know is that if the AM5 socket will retain the locking mechanism or the mounting holes. At this point, it's anyone's guess whether consumers will need to invest in a new cooler, or if existing cooling solutions are still viable with a mounting converter kit.
If they are keeping the socket size the same as AM4, I would suspect they would probably want to maintain backward compatibility with existing aftermarket coolers to keep the transition as smooth as possible. Intel might be breaking cooler compatibility with Alder Lake, but they are changing the dimensions of their socket, and that will be after maintaining compatibility with existing coolers for over 13 years by that point. I can't see AMD breaking cooler compatibility with AM5 just 5 years after requiring manufacturers to update their mounting hardware for AM4 if they can help it. Unless their LGA socket design requires the processor to be mounted at a different height or something, I would think they wouldn't make any changes.
AMD still needs to cater to lower Core Markets / Budget markets.
Making a new Die Mask for 4x Core & 6x Core CCX's makes sense.
Especially as yields for 8-cores are getting better over time.
The yields are likely be getting better for 7nm chips, but they should be moving to the 5nm process node for Zen 4, and I doubt there's any verifiable information publicly available about what the yields for these chiplets will be like on that node. Not as good as on 7nm is probably a safe bet though.
Also, I don't see the point of 4-core chiplets. The only 4-core non-APU processors AMD has launched after the 1000-series have been either OEM-only parts, or parts that were only available in very limited quantities, based on chips that didn't meet the standards for higher-core parts. Currently, AMD has the same chiplets used all the way from their mainstream processors up to their server parts, and that gives them more flexibility to bin chips based on their characteristics for different processors. And they probably wouldn't want to mix chiplets of different core counts, since that would mean different cores would have access to different shared cache capacities. No one is likely to pay a big premium for a high-binned quad-core at this point, so that silicon would be wasted for low-end chips, and any quad-core chiplet with a defective core would need to be sold as something like a dual-core, which is probably a waste to use a chiplet design for. And most of those picking up budget quad-core and dual-core chips, especially in 2022 and beyond, are likely to be using them with integrated graphics. Though I suppose I could see them adding integrated graphics to the IO chip to enable IGPs across the lineup. Really though, there probably wouldn't be much benefit from manufacturing budget desktop parts on the latest node unless they used the same silicon as their laptop processors, and those are more likely to remain as monolithic chips for the time-being.
That being said, 12-cores seems like a lot to put in a chiplet, and having only 12-core chiplets would probably not be a very efficient way to do things, at least if they plan on using multi-chip designs for their 6 and 8-core parts. Maybe having 12-core and 6-core chiplets could make some sense, though I would not be surprised to see them stick with 8-cores per chiplet for their Zen 4 lineup. They will be making a lot of changes to their processors and platform, and saving a core-count boost per chiplet for a future generation might make more sense. After all, the vast majority of today's desktop usage scenarios tend to see little benefit from moving from 6-cores up to 8, let alone 12, so I'm not sure there's enough demand for 12+ core desktop processors outside of relatively niche markets, and it seems unlikely that will change much in the next year.
A 3 chiplet configuration I can't picture because of the problem trying to make the dies equidistant from the I/O die to ensure equal latency without doing something dumb-sounding like lengthening the traces for the other two chiplets.
I don't see why that would necessarily be a problem. They could likely rotate the chiplets 90 degrees and fit three side-by-side, especially if the IO chip were a bit narrower. A smaller IO chip might also be positioned in a more centralized location, with chiplets positioned on three sides, for example.
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