News Mockup of AMD's Zen 4 Raphael CPU Appears With Potential Specs

[InvalidError]

CCX generally refers to the individual CPU Cores on the dies that are cut from the waffer.

CCD refers to the packaging holding all the Dies together into one Polymer package that eventually gets bonded to the CPU substrate via BGA.

That's how I've been using the definition.

Then you have the wrong definitions.

A CCX in AMD jargon is a handful of cores and a chunk of L3$ sharing a stop on the Intinity Fabric.
A CCD in AMD jargon is literally a Core Complex Die which may contain more than one CCX sharing one IF link with the IOD.

The combination of however many CCDs and one IOD sharing a package substrate is just an assembled package, there is no special jargon for it.

I don't think AMD would integrate the IGPU into the IOD, that's unnecessary complexity.

AMD would most likely make it's own IGPU chiplet and use a empty Chiplet(CCD) Slot to place it in.

That's far simpler and more flexible than to merge a IGPU into the IOD.

What would be unnecessary complexity is wasting 20mmsq of IGP chiplet die on an IF controller and another 20mmsq in the IOD for an IGP that is only 40mmsq itself. Having the IF fabric latency added to the IGP's every memory IO would likely hurt performance quite significantly too - the IF latency is why AMD had to double L3$ sizes on Zen 2 and also why its monolithic APUs can beat their nearest equivalent CPU-only counterparts despite having 1/4 as much L3$.

Here, the 5600G beats the 5600X on single-core performance (at least those I have seen online) by about 15% while losing by about 8% on multi-core.

View: https://youtu.be/7AZYrQ21PLE

 

[Kamen Rider Blade]

What would be unnecessary complexity is wasting 20mmsq of IGP chiplet die on an IF controller and another 20mmsq in the IOD for an IGP that is only 40mmsq itself. Having the IF fabric latency added to the IGP's every memory IO would likely hurt performance quite significantly too - the IF latency is why AMD had to double L3$ sizes on Zen 2 and also why its monolithic APUs can beat their nearest equivalent CPU-only counterparts despite having 1/4 as much L3$.

Having to bin their IOdies based on IGPU quality and having to seperate it out would be unnecessary work when the point of the IO die is to be a simple Switch for data.

I wouldn't be surprised if more of the IOD Transistor RealEstate space is used for increasing the PCIe lane count and other IO features that they want to connect.

IGPU isn't that high of a priority for DeskTop and making the IGPU it's own Chiplet module allows for simpler flexibility when adding it to the product stack since it would eat a empty CCD space and create a new SKU via that route.

If AMD wanted to create a integrated IGPU, they already have the APU.

The whole point of the Chiplet design is to seperate the parts and make it easy to modularly add/remove features to the Product stack in short order and time to market.

Same with the merger with Xilinx and adding a FPGA Chiplet to connect to the IOD.

Or a dedicated AI Chiplet.

The whole point isn't to complicate the IOD by adding more dedicated functionality at that piece of Silicon.

The point is to modularize like Legos, as much as possible, and connect via Infinity Fabric.

And yes, there are some penalties to doing that, but AMD has long accepted it and used L3$ to mask the latency penalties.

That's the whole point of "Chiplets".

 

[TJ Hooker]

CCD refers to the packaging holding all the Dies together into one Polymer package that eventually gets bonded to the CPU substrate via BGA.

This is incorrect. CCDs are individuals dies (Core Chiplet Die), they have nothing to do with packaging/substrate. CCXs are clusters of cores than share L3. Previously CCXs had 4 cores, and therefore an 8 core CCD had two CCXs (Zen 2). For Zen 3 AMD went to 8 core CCXs. This is all in the article you linked. So for Zen 3, "CCX" and "CCD" can often be used interchangeably.

As far as packaging goes, I'm not aware of any additional "polymer packaging" being used. The dies are mounted directly on the substrate, they aren't mounted to any intermediate interposer-like material.

 

[Kamen Rider Blade]

As far as packaging goes, I'm not aware of any additional "polymer packaging" being used. The dies are mounted directly on the substrate, they aren't mounted to any intermediate interposer-like material.

The polymer packaging is the shell that holds the dies together, before it gets bonded to the substrate.

 

[InvalidError]

The whole point of the Chiplet design is to seperate the parts and make it easy to modularly add/remove features to the Product stack in short order and time to market.

There is a point where functionality becomes too small to be viable as its own separate thing, especially when said functionality requires the lowest-latency and highes-bandwidth possible to system RAM for decent performance.

The polymer packaging is the shell that holds the dies together, before it gets bonded to the substrate.

Underfill is added AFTER the dies have been soldered to the substrate to protect the tiny solder joints.

 

[Kamen Rider Blade]

Then you have the wrong definitions.

A CCX in AMD jargon is a handful of cores and a chunk of L3$ sharing a stop on the Intinity Fabric.
A CCD in AMD jargon is literally a Core Complex Die which may contain more than one CCX sharing one IF link with the IOD.

The combination of however many CCDs and one IOD sharing a package substrate is just an assembled package, there is no special jargon for it.

AMD CCD and CCX in Ryzen Processors Explained

AMD’s Ryzen CPUs are made up of core complexes called CCDs and/or CCXs. But what is a CCX and how is it different from a CCD in an AMD processor? Let’s have a look. There are many factors responsible for AMD’s recent success in the consumer market. But, the chiplet or MCM design (Multi-chip...

www.hardwaretimes.com

My usage of CCX is closer to HardwareTimes definition.

The basic unit of a Ryzen processor is a CCX or Core Complex, a quad-core CPU model with a shared L3 cache.

However, while CCXs are the basic unit of silicon dabbed, at an architectural level, a CCD or Core Chiplet Dies are your lowest level of abstraction. A CCD consists of two CCXs paired together using the Infinity Fabric Interconnect. All Ryzen parts, even quad-core parts, ship with at least one CCD. They just have a differing number of cores disabled per CCX.

 

[Kamen Rider Blade]

There is a point where functionality becomes too small to be viable as its own separate thing, especially when said functionality requires the lowest-latency and highes-bandwidth possible to system RAM for decent performance.

Yet AMD has managed to pull it off with the CCX/CCD concept.

I'm sure they can pull it off with IGPU's, FPGA's, Dedicated AI ASIC's packaged into Chiplets.

It's like the Apple M1 Approach, included dedicated hardware for ___ functionality to speed up functionality for local end user / consumer.

It's not meant to be the "Best" in the world, it just needs to be good enough for the job at hand.

Dedicated FPGA boards, Graphics Cards, AI Boards will all be "Superior" at their dedicated jobs since they have and entire Add-On Board with more power and local memory to do their jobs.

Chiplets were never meant to compete with those dedicated add-on cards.

The whole Chiplet approach is to be flexible to respond to market competition.

Like Apple M1, you can add in Chiplet modules to be "Good Enough".

the IGPU chiplet was never meant to be a "World Beater" or "Amazing".

It just has to be good enough to compete with Intel's & Apple's IGPU's.

That's not asking for much in all honesty.

 

[Kamen Rider Blade]

As far as packaging goes, I'm not aware of any additional "polymer packaging" being used. The dies are mounted directly on the substrate, they aren't mounted to any intermediate interposer-like material.

I never used the word "Interposer".

It's like how RAM dies are put inside the Polymer packaging that surrounds the Die, before the Die gets bonded to the PCB substrate via BGA.

 

[TJ Hooker]

The polymer packaging is the shell that holds the dies together, before it gets bonded to the substrate.

Source? I'm looking at this, nothing about any "polymer packaging", the dies attach directly to the substrate via solder bumps.

 

[hotaru.hino]

Well to put a stick in the "AMD should support lower end" mud: Lisa Su announced no plans to address the lower end market with Zen 3 any time soon due to a lack of manufacturing capacity. https://www.windowscentral.com/amd-ceo-talks-chip-shortage-and-prioritizing-high-end-gpus

But again, AMD can just harvest from defective 8-core dies as needed if they really wanted to make a lower end product like they've always had.

Because it's part of their product stack, to eventually cover the low end.

Why does NAVI 20 or NAVI 10 come in multiple dies, to cover multiple parts of the market.

Eventually as AMD sells more Cores and increases the Core Count for Ryzen 9, there has to be a bottom limit.

That bottom limit has already been historically established as 4-cores.

Intel's i3 10,000 series and Ryzen 3 3000 series

And CPU & APU will co-exist, just like in the 3000 series time frame.

The only reason it doesn't exist now is because COVID-19 has thrown everything in a loop and everybody's schedule is out of whack.

Because Demand OutrStrips Supply, both AMD & Intel only bother with their High End & Mid-Range part of their new product stack.

And usually the bottom part of the stack is always "Last" to come out with little to no fanfare.

Again the problem with making another die is they at the minimum have to make another set of die masks which as far as I can tell on a short trip to Google University, isn't exactly cheap. This is on top of the proving out and testing the thing. This is also assuming that AMD designed the chiplets with such modularity in mind in the first place. If it's cheaper to simply make a bunch of 8-core chiplets and harvest a number of them for the lower end market than it is to ramp up production for said SKU, then there's no point. Plus again: a standalone 4-core processor makes little sense when its competition includes an iGPU. Discrete CPU + Video card is always going to be more expensive than a CPU with an iGPU and the only real market I see a standalone 4-core processor for are budget gamers, which no matter how much you want to believe gamers are a big market, they really aren't in the face of businesses and casual computer users.

 

[Kamen Rider Blade]

Source? I'm looking at this, nothing about any "polymer packaging", the dies attach directly to the substrate via solder bumps.

https://www.anandtech.com/show/1614...en-3-on-nov-5th-19-ipc-claims-best-gaming-cpu

I'm literally looking at the Polymer Packaging that encapsulates the CCX's and the IOD

https://images.anandtech.com/doci/16148/1 Carou.jpg

The Solder Bumps are the conectors between the Polymer Packaging to the PCB Substrate that links everything together.

 

[InvalidError]

My usage of CCX is closer to HardwareTimes definition.

The basic unit of a Ryzen processor is a CCX or Core Complex, a quad-core CPU model with a shared L3 cache.

The "quad core" 'definition' does not apply to Zen 3, Zen 3 has 8 cores per CCX and one CCX per CCD, unlike Zen 1 and 2 which had quad-core CCX and two CCX per chip. You need to use the correct definition for the specific generation you are talking about. For current-gen, CCDs and CCXes on those CCDs are 8-cores with a single shared L3$.

Yet AMD has managed to pull it off with the CCX/CCD concept.

They haven't made CCDs smaller than 80mmsq and may never will: the cutting lines between dies is around 1mm wide and every time you cut a 9x9mm square, you lose around 20mmsq of wafer space cutting it. If you make even smaller chips, the amount of wafer space lost to cutting gets even worse. So it makes the most sense for AMD to increase the core count per CCD as individual cores get smaller to balance cutting losses against yields.

 

[Kamen Rider Blade]

Well to put a stick in the "AMD should support lower end" mud: Lisa Su announced no plans to address the lower end market with Zen 3 any time soon due to a lack of manufacturing capacity. https://www.windowscentral.com/amd-ceo-talks-chip-shortage-and-prioritizing-high-end-gpus

But again, AMD can just harvest from defective 8-core dies as needed if they really wanted to make a lower end product like they've always had.

Su continued, "Here is some compute that we're leaving under serviced ... if you look at some of the segments in the PC market, sort of the lower end of the PC market, we have prioritized some of the higher-end commercial SKUs and gaming SKUS and those kinds of things."


AMD prioritized higher-end CPUs to meet the demands of customers. Su explained that at the moment, supply chains focus on delivering what end customers want, not filling up shelves.


The global chip shortage has made it difficult to purchase both CPUs and GPUs from both the high-end and low-end. As a result, anyone that wants to build their own PC struggles to do so at a budget.

I agree with Lisa Su & Jen-sen Huang.

When there is a shortage and Demand outstrips supply, you target the high end of your product stack and leave the low end hanging.

Everybody is doing this, From AMD/NVIDIA/Intel.

That's no surprise to anybody who is paying attention.

If I were in their shoes, I would do the same thing.

Low End Product Stack with Low Margins will always be Last Priority.

That's just the nature of economics.

 

[TJ Hooker]

https://www.anandtech.com/show/1614...en-3-on-nov-5th-19-ipc-claims-best-gaming-cpu

I'm literally looking at the Polymer Packaging that encapsulates the CCX's and the IOD

https://images.anandtech.com/doci/16148/1 Carou.jpg

The Solder Bumps are the conectors between the Polymer Packaging to the PCB Substrate that links everything together.

You mean the glossy stuff around the edges of the dies? It looks like you're referring to the polymer underfill that InvalidError described? That may be part of the overall packaging process, but nobody would refer to that polymer underfill as being a "package".

 

[Kamen Rider Blade]

The "quad core" 'definition' does not apply to Zen 3, Zen 3 has 8 cores per CCX and one CCX per CCD, unlike Zen 1 and 2 which had quad-core CCX and two CCX per chip. You need to use the correct definition for the specific generation you are talking about. For current-gen, CCDs and CCXes on those CCDs are 8-cores with a single shared L3$.

That's currently, who knows what will change in the future.

And if the 12 Core CCD is coming, I wouldn't be surprised if a 8 Core CCX & 4 Core CCX gets packaged together under one CCD like CCD's of earlier generation.

The 8 Core / 4 Core / 12 Core market are all seperate markets.

And yields are getting better, I doubt there are that many more 8 Cores that will need to be binned down to 6 Cores.

Having a dedicated 6 Core CCX would allow them to build to 12 Cores per CCD in the future and allow variability in # Cores per CCD.

Eventually they'll have one dedicated 12 Core CCX placed in one CCD, but that's going to be a top end part.

There will be other methods to build a 12 Core CCD that isn't from the Top End part.

Just like AMD in the past has made a 4 Core CCD out of two Quad-Core CCX's that were binned down to 2 Cores each and paired together under one CCD.

I wouldn't be surprised if in the future that the pure 12-Core CCD with 1x 12 Core CCX would be the top of the product stack and every variant that gets "Glued" together like the old days becomes a lower tier product stack.

12-Core CCD
Top Tier
Variant 1: 12 = 12
Variant 2: 8+4=12
Variant 3: 6+6= 12
Variant 4: 4+4+4 = 12
Bottom Tier

 

[Kamen Rider Blade]

You mean the glossy stuff around the edges of the dies? It looks like you're referring to the polymer underfill that InvalidError described? That may be part of the overall packaging process, but nobody would refer to that polymer underfill as being a "package".

I'm not talking about the UnderFill.

https://www.mccoycomponents.com/blog/view/understanding-chiplet-in-one-article

Polymers in Electronic Packaging: Introduction to Semiconductor Substrates - Polymer Innovation Blog

Figure 1. Cross section of PBGA package showing a multilayer semiconductor substrate (Source: NXP Freescale) A previous post described the plastic ball grid array (PBGA) package. This post will provide an introduction to semiconductor substrate technology. In Figure 1, the semiconductor...

polymerinnovationblog.com

The polymer packaging that I was talking about is the Epoxy Overmold that surrounds the Silicon Die and protects the Copper Bonded Wires that connect to the Substrate which connect to the PCB beneath it via BGA.

All modern Chips are generally packaged in some form of Polymer, in this case, a Epoxy Overmold.

https://en.wikipedia.org/wiki/Epoxy
Epoxy resins, also known as polyepoxides, are a class of reactive prepolymers and polymers which contain epoxide groups.

That's why I call it the Polymer Packaging, because Polymer literally encases the Silicon Die and any Copper Bonded Wires to the Substrate that will eventually be connected to the PCB via BGA.

 

[InvalidError]

All modern Chips are generally packaged in some form of Polymer, in this case, a Epoxy Overmold.

No. Epoxy overmold has been mostly obsolete for high-density high-power ASICs since FC-BGA which eliminates bond wires and replaces them with solder balls that connect pads on the die directly to pads on the substrate. The back of the die is directly exposed so it can either be bonded to an IHS or a heatsink can be put on top.

Bond wires are still used for lower-power, lower-density stuff like stacking NAND and DRAM chips to avoid interposers and TSVs.

 

[TJ Hooker]

https://www.mccoycomponents.com/blog/view/understanding-chiplet-in-one-article

This link doesn't mention anything about a polymer package. If you look at the diagram for MCM, it shows the dies connected directly to the substrate via solder bumps.

Polymers in Electronic Packaging: Introduction to Semiconductor Substrates - Polymer Innovation Blog

Figure 1. Cross section of PBGA package showing a multilayer semiconductor substrate (Source: NXP Freescale) A previous post described the plastic ball grid array (PBGA) package. This post will provide an introduction to semiconductor substrate technology. In Figure 1, the semiconductor...

polymerinnovationblog.com

The polymer packaging that I was talking about is the Epoxy Overmold that surrounds the Silicon Die and protects the Copper Bonded Wires that connect to the Substrate which connect to the PCB beneath it via BGA.

All modern Chips are generally packaged in some form of Polymer, in this case, a Epoxy Overmold.

Your second link is about packages that use wire-bonding. No idea why you think that applies to all modern chips but it doesn't, and it certainly doesn't apply to AMD CPUs (which use flip-chip). If the die was completely enclosed in polymer that would essentially form an insulating layer between the die and the heatspreader, which would be bad for cooling a high powered chip like a CPU.

 

[Kamen Rider Blade]

No. Epoxy overmold has been mostly obsolete for high-density high-power ASICs since FC-BGA which eliminates bond wires and replaces them with solder balls that connect pads on the die directly to pads on the substrate. The back of the die is directly exposed so it can either be bonded to an IHS or a heatsink can be put on top.

Bond wires are still used for lower-power, lower-density stuff like stacking NAND and DRAM chips to avoid interposers and TSVs.

Your second link is about packages that use wire-bonding. No idea why you think that applies to all modern chips but it doesn't, and it certainly doesn't apply to AMD CPUs (which use flip-chip). If the die was completely enclosed in polymer that would essentially form an insulating layer between the die and the heatspreader, which would be bad for cooling a high powered chip like a CPU.

IC

 

[hotaru.hino]

And if the 12 Core CCD is coming, I wouldn't be surprised if a 8 Core CCX & 4 Core CCX gets packaged together under one CCD like CCD's of earlier generation.

I don't see why they would go back to 4-core CCXes given why they went to 8-core for Zen 3:

 

[Kamen Rider Blade]

I don't see why they would go back to 4-core CCXes given why they went to 8-core for Zen 3:

The consumer market isn't one-size fits all.

And they need parts to target the lower end market eventually.

8-Core CCX's are the high end Dies for Zen 3.

Eventually, when they need to target the low end of the product stack, they'll reveal the 4-Core CCX for that market.

Just like NAVI has multiple dies, Zen will eventually have multiple Dies.

 

[Karadjgne]

It's all about the price. If you look at a 5800x, that's 8cores on 1x 8core CCX. And priced somewhat above where it should be in the stack as a result. It has 0 room for error, if even one core fails QC, you've got a 5600x instead as AMD will burn that core and the worst core of the rest. Using 2x 6core CCX instead would overall be better as upto 4 cores could fail. (5900x). It also frees up real-estate under the IHS, lowers heat outputs having just 6 cores per chiplet vs 8 etc.

So there are arguments to be had in both directions.

The article failed to mention the single most important reason to switch to LGA from PGA. LGA has a viable locking mechanism that PGA sockets don't have. Totally solve the 'cpu stuck to the cooler by paste' mishaps and damages.

 

[InvalidError]

8-Core CCX's are the high end Dies for Zen 3.

Eventually, when they need to target the low end of the product stack, they'll reveal the 4-Core CCX for that market.

Nope. Last week, Lisa Su has basically confirmed that there won't be low-end Ryzen 5000 parts due to no wafers to spare to make them. The 5xxxG shortage is so bad that most OEMs that had them have discontinued them. You likely won't be able to get a Ryzen 5xxxG until AMD has shifted a good chunk of its demand to Ryzen 6000 SKUs on 5nm to free up some 7nm.

 

[hotaru.hino]

The consumer market isn't one-size fits all.

And they're not doing that. That's the point of their chiplet strategy. Rather than make dies for each market segment, build the smallest feasible die and tack on more as needed. If the "smallest feasible" is an 8-core die, then so be it.

Eventually, when they need to target the low end of the product stack, they'll reveal the 4-Core CCX for that market.

I don't see what benefit this brings. If this is for a native 4-core die, then what's the point? Unless it's in an APU, system builders aren't really going to be interested in it because it means needing a video card which adds cost and there goes the point of having a low-cost computer. And in my mind, it would make sense to only relegate it to the lower end. If you try to build higher end SKUs with it, such as a 6-core or an 8-core, then there's cross CCD latency which will hamper performance compared to the single die variants. And there's a higher manufacturing cost because you're adding yet another thing on the package. Then pricing becomes a problem: too low and it's not profitable enough, too high and nobody wants it because the single die variants are better.

Just like NAVI has multiple dies, Zen will eventually have multiple Dies.

Because GPUs are still built on monolothic processes. If/when AMD makes a chiplet version of their GPUs, I'm willing to wager they'll only make one configuration per die because it's the most cost-efficient way to do things.

 

[Kamen Rider Blade]

Nope. Last week, Lisa Su has basically confirmed that there won't be low-end Ryzen 5000 parts due to no wafers to spare to make them. The 5xxxG shortage is so bad that most OEMs that had them have discontinued them. You likely won't be able to get a Ryzen 5xxxG until AMD has shifted a good chunk of its demand to Ryzen 6000 SKUs on 5nm to free up some 7nm.

Then it'll come back when Waffer capacity exists to make it.

I don't expect it to be anytime soon until the Chip Shortage is solved.

And they're not doing that. That's the point of their chiplet strategy. Rather than make dies for each market segment, build the smallest feasible die and tack on more as needed. If the "smallest feasible" is an 8-core die, then so be it.

The "Smallest Feasible" die would be a 4-core die like last gen with the Ryzen 3000 series.

But right now is a special circumstance thanks to COVID-19 & Chip Shortage.

I don't see what benefit this brings. If this is for a native 4-core die, then what's the point? Unless it's in an APU, system builders aren't really going to be interested in it because it means needing a video card which adds cost and there goes the point of having a low-cost computer. And in my mind, it would make sense to only relegate it to the lower end. If you try to build higher end SKUs with it, such as a 6-core or an 8-core, then there's cross CCD latency which will hamper performance compared to the single die variants. And there's a higher manufacturing cost because you're adding yet another thing on the package. Then pricing becomes a problem: too low and it's not profitable enough, too high and nobody wants it because the single die variants are better.

Single Die Variants will be the top of the product stack while lower "Glued" together cores will be lower end of each product stack.

You're thinking in such a short near sighted product range.

I'm thinking of eventually when they build Ryzen parts up to 24 Cores for Consumers with a SKU with different core counts each.
Everything ranging from 4/5/6/7/8/9/10/12/14/16/18/20/22/24 cores for consumers to choose from.

That flexibility with multiple CCX's lets you create the SKU you'll need based on mixing & matching + binning.

And, eventually EPYC/ThreadRipper with 8x CCD's can go all the way up to 96 Cores with all sorts of SKU's in between.

The point of having 4/6/8/12 Core dies is to mix & match to get the Core Count & Performance that you want for the consumer base that wants a specific configuration.

Especially with Server SKU's that have different virtualization needs.

Some VM's will be primarily 4-Core based, some will be 6-Core based, others will be 8-Core based, and some will be 12-Core based.

And when you can scale things as needed based on customer workload, you'll have a solution for each situation.