Do you even read the things you post about or are you 100% driven by make believe?
Yes, I do read what I post about. And, by now, you know very well that I choose my words carefully.
The claim I was responding to was:
Any code made for APX will still run on any old CPU just slower and less efficient.
See where you said "any code"? That's a
very strong statement and it's
different than what you're arguing now.
You need to use new prefixes, if a dev wants to use legacy instructions using the new method they will be able to by adding them.
Yeah, but no. I've used explicit prefix bytes in assembly code to override 32-bit vs. 16-bit. This is not like that. It's not just a
fixed opcode byte that you add, but rather one that you'd have to
custom compute for each instruction, according to which registers it uses.
This still passes through the compiler and if the compiler is set to compile for an old CPU it will not include the optional things
Um, no. You can't take assembly code written for using 32 General Purpose Registers and 3-operand instructions, simply exclude the REX2 prefix byte and have it work properly with 16 GPRs + 2-operand instructions.
This also doesn't apply to any higher-level languages. In that case, you're 100% dependent on the compiler to generate code for the selected target. On the plus side, you're also not manually computing prefix bytes.
So intel staying stagnant is a clear admission of them being well ahead...don't you see how crazy your argument is?!
Crazy like a fox!
🦊
All CPU makers ARM included constantly search and adopt things to make them faster and more efficient, is ARM admitting defeat because they add new things?
ARM made the move to 32 GPRs back in 2011, when they announced AArch64 (the 64-bit version of their ISA). They already had 3-operand instructions. They haven't made any wholesale changes to their instruction set, since then.
As I said, it's one thing to add new instructions, but another thing to retrofit an existing ISA with wholesale new capabilities. In the case of APX, it comes at the expense of instruction stream density. AArch64 instructions are all a nice 4 bytes in length. In the case of x86-64, I'm reading the maximum instruction length was 15 bytes, which the new prefix bytes presumably increases to 16 bytes.
That affects everything from how much room instructions burn in the cache hierarchy, how much memory bandwidth is chewed up by fetching instructions, how big and power-consuming the instruction decoders get, and how far ahead the instruction decoders have to search for the next instruction. It's not nothing.