Lots of buzzwords...
One interesting thing with the RISC-V spec. is that instead of having a fixed-width SIMD instruction set similar to Intel AVX2 and ARM Neon, it has a vector instruction extension where the vector-length is an implementation detail. It also support vector-lane masking. An implementation with very wide vectors and masking would make it quite similar to how GPUs from AMD and NVidia do computation.
Neox could have that ... or it could have a more or less custom ISA. (There have been RISC-V CPUs with weird vector units before)
BTW. ARM also has a scalable vector extension in addition to Neon. But few chips have also implemented it so far.
"Deep learning"/"AI" unit usually means simply that it is capable of doing parallel multiply-adds with 16-bit floating point factors and 32-bit sums. That could maybe be parallelised into dot products or full multiplications with fewer instructions but there is no way of knowing which from just buzzwords.