P4 at 2.2 and memory

[IIB]

yes, but will DDR400 have half the lathncy of DDR200? its frequancy scaling... just like RDRAM is going from 800 to 1066...

 

[Matisaro]

C) Bandwidth is measured per pin, not per 'channel'. Channels are an arbitrary term. Pins are what take up space on the motherboard. i850 uses 32-pins total for RDRAM channels. A 'dual-channel DDR SDRAM' chipset would use 128-pins total for DDR SDRAM channels. This is less bandwidth per pin. For the same amount of real-estate on the motherboard you could instead use 128-pins for RDRAM and get much more memory bandwidth.

D) PC1066 RDRAM will have less latency than your DDR SDRAM solution. (PC1066 RDRAM has exactly 3/4 the latency of PC800 RDRAM. DDR SDRAM does not scale in such a linear fashion.)

C: that matters to the mobo manufacturers not us, we would require more memory modules to use this extra bandwith per pin, which would increase OUR cost.

D: you were proven wrong on this in other threads, pc1066 does NOT have lower latency than ddrsdram, so stop spreading FUD raystonn.

"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!

 

[Matisaro]

A: ddr sdram does NOT run internally at 200mhz, it merely sends data on the rising and falling edge of the clock, the internal transistor speeds are the same as in pc100 and pc133. Your assertion that latency decreases as you increase bandwidth is wrong, it decreases are you increase CLOCK SPEED. This is supported by this article and quote.

"SDRAM and DDR SDRAM use a different approach, by using a parallel databus, 64 bits wide; adding modules to the system has no negative effect on memory latency. In addition to the 64-bit databus, the memory controller must drive a multiplexed row and column address to the SDRAM with the control signals. Typical latency is 10 ns for both PC100 SDRAM and PC1600 DDR SDRAM, and 7.5ns for both PC133 SDRAM and PC2100 DDR SDRAM. "

<A HREF="http://www.hardwarecentral.com/hardwarecentral/reviews/2445/4/" target="_new">http://www.hardwarecentral.com/hardwarecentral/reviews/2445/4/</A>

The latency is the same, because the internals of the chip are the same.


Even more evidence for this.

DDR DRAM is basically just a more advanced flavor of SDRAM, with an added twist at the data pins. If you recall the SDRAM timing diagrams from the previous RAM Guide, you'll know that SDRAM transfers its commands, addresses, and data on the rising edge of the clock. Like regular SDRAM, DDR DRAM transfers its commands and addresses on the rising edge of the clock, but unlike SDRAM it contains special circuitry behind its data pins that allows it to transfer data on both the rising and falling edges of the clock. So DDR can transfer two data words per clock cycle, as opposed to SDRAM's one word per clock cycle, effectively doubling the speed at which it can be read from or written to under optimal circumstances. Thus the "DDR" in DDR DRAM stands for "Double Data Rate," a name that it gets from this ability to transfer twice the data per clock as an SDRAM.

Another way to think about the need for multiple banks is to think of it all in terms of keeping the data bus full. If a 64-bit wide data bus is being run at 100MHz, then it has a lot of clock pulses flying by on it every second. Since two words of data can ride on a single clock pulse (one word on the rising edge and one word on the falling edge), the bus has a lot of potential clock pulses open every second that are available to carry pairs of 64-bit data chunks. So think of each clock pulse as having two empty slots that need to be filled, and think of the 100MHz bus as a conveyor that carries those pairs of slots by at a good clip. Now, if there were only one bank of memory, then there could be only one row open on each DIMM. If you had a system with only 1 DIMM then that one row would have to put out enough data every second to fill up all of those slots. Since memory accesses often move around from row to row, that's not likely to happen. That one bank would have to keep switching rows, and since switching rows takes time, a lot of those clock pulses would have to fly by empty-handed while the bank is doing its switching.

The only difference between sdram and ddrsdram is a small amount of logic behind the data pins, as you can see in this well written article.
<A HREF="http://arstechnica.com/paedia/r/ram_guide/ram_guide.part3-1.html" target="_new">http://arstechnica.com/paedia/r/ram_guide/ram_guide.part3-1.html</A>

One point countered, ray why do you expect us to buy you tested tons of ddr modules and proved them to be corrupt when slightly overclocked if you dont even understand how they work.

"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!

 

[Matisaro]

It is in fact doubling the clock speed in the SDRAM itself. Data is transferred twice per memory clock. One data transfer must be complete before the next can begin. Thus, data transfers are in fact taking place in half the time between memory and the processor.

-Raystonn

Proven wrong in the above post, ray perhaps you should read the article I linked to, it explains how ddr sdram REALLY works.

"The Cash Left In My Pocket,The BEST Benchmark"
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[Matisaro]

Memory latency expressed as a number of memory clock cycles actually remains exactly the same for RDRAM. The clock cycles being used as the unit value there are processor clock cycles

I believe it is actually fsb cycles, not cpu cycles. This article seems to support my assertion, but I cannot find any deffinative answer to that.

http://www.aceshardware.com/Spades/read.php?article_id=140

But it is not clear, Need to find more links.


"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!

 

[Matisaro]

Ahhhh, heres some good benchmarkin.


When you look at clockspeed, which is the right way to assertain if latency should drop, and not bandwith which someone has said, you get these results.

(no ddr only sdram)

http://www.hardocp.com/articles/memory/ddrovr/index3.html

Specifically this table.

Memory Type
Average Latency (ns)
Average BW (MB/s)

SDRAM



PC100 (3:3:3)
55.2
376

PC100 (2:2:2)
36.8
479

PC133 (3:3:3)
41.4
501

PC133 (2:2:2)
27.6
639

PC150 (2:3:2)
29.2
650

PC166 (2:3:2)
26.3
723





WHATS THIS! Why as CLOCKSPEED increases, the memory latency decreases just as it does for rambus. And an increase of 33% clock speed, netted a decrease of 25%(pc100 2.2.2 > pc 133 2.2.2) Which is rather close to the rambus figures.

There is no reason to believe that this linearity would not continue in ddr which as I have proven above, is fundamentally the same as sdram with a small signal pin change.

Looks like every assertion ray made was wrong.


PS: If anyone thinks im riding rayy hard, its because he accused me of spreading fud in another thread and im not too pleased about it.

Rayy, counters, any links you can provide...defence?

"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!

 

[mala]

Sure it is. The memory itself is operating at a frequency of 200MHz. The interface (bus) from the memory to the chipset's memory controller is operating at 100MHz, but transmitting twice per clock. If DDR is only marginally better than SDR in terms of latency, then QDR would be only marginally better than DDR in terms of latency. Latency would really be hurting it. Meanwhile RDRAM is scaling up using frequency...

Yes, your are right. QDR, ODR et.c would have about the same latency as DDR. But this has nothing to to with JEDEC vs RAMBUS. RAMBUS also uses a DDR philosophy. If there ever was a SDR RDRAM standard (which I doubt) I'm sure the latencies was about the same as the DDR one.
AFAIK DDR was 'invented' to be able to increase the bandwidth without having to deal with latency. That, plus you save some power by not sending clk (two edges) for every data (at most one change ~~ edge).

You could mean two (and more) things by latency.
One is the latency from when the read command arrives at the DRAM logic to the point where the first data leaves the chip. This is what I was talking of above.

The other is when the processor demands a cacheline from the memory subsystem (because in reality you always read 2^N bytes at a time) to where the complete cacheline is transferred to the CPU.

In the second "real life" definition a large part of the latency is actually the term <b>cacheline_size/(memory_frequency * bytes_per_transfer * transfers_per_clock)</b>. This will of course benefit from high bandwidth, QDR, DDR, higher pin count AND higher frequency.

The first definition, which is also a term in the second, will only depend on the frequency and DRAM-timings.

Right. However, they were unable to keep the timings constant. SDRAM simply cannot keep up. Its parallel nature causes more problems and makes it more difficult to ensure no signal conflicts.

You are probably right about the parallell thing. The industy is going towards serial solutions in other areas (USB, serial ATA et.c). So I agree RDRAM has a better potential of achieving high _bandwidth_ in a system.

The parallell nature of SDRAM will maybe be a problem when trying to maximize bandwidth, but it will not have an impact on the DRAM timings, because the DRAM-chip itself does not know what interface it is connected to. When I say the "DRAM chip" I mean the memory array and the old school DRAM-logic. Itegrated on the chip is also the Synchronous control logic which does the IO, but it isn't involved very much in the actual memory access.

The complete latency equation is too complicated for me to grasp, and DDR and RDRAM has some differences in how often a read will result in the worst case, best case et.c. For example I think you wrote somewhere that RDRAM has less penalty when doing a read after a write.

But with a pure increase in frequency the math is simple. If you raise the frequency with all things equal (overclock) the latency will be about 1/oc. And I think that if the same company makes a RDRAM-chip and a DDR-chip in the same factory with the same maufacturing process, they would be able to make the timings the same for both chips.

To sum it up. RDRAM and DDRSDRAM has some differences, but I think they have more in common than people think. When reading "My RAM is better than yours"-threads one could get the impression that RDRAM is from mars and DDR is from Venus... They are NOT. Both originates from Earth. =)

 

[Raystonn]

that matters to the mobo manufacturers not us, we would require more memory modules to use this extra bandwith per pin, which would increase OUR cost.

Actually no. 32-bit and 64-bit RDRAM modules are on the roadmaps. This would remove the requirement of needing more than a single memory module per 64 pins.

If we restrict the discussion to what is available today, then we only get 16 pins per memory module. However, if we do that, then the whole discussion on dual-channel DDR SDRAM is excluded from consideration, as it is not available today, nor on any roadmaps.

pc1066 does NOT have lower latency than ddrsdram

That depends entirely on the speed of the DDR SDRAM, along with the platform in question. At worst, PC1066 RDRAM has about the same latency as PC2100 DDR SDRAM on the same platform. In other comparisons, it shows as having less latency.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =

 

[Kelledin]

If we restrict the discussion to what is available today, then we only get 16 pins per memory module.

One interesting detail that no one seems to have mentioned is that while the <i>theoretical</i> pin count should be different between RIMMs and DDR DIMMs, they are both listed as 184-pin parts.

So the extra pins on RIMMs are for what--to account for greater power consumption? To account for additional required control lines? How many are power lines, and how many are data lines? How many terminate at the memory controller of the chipset's northbridge? At first glance, it seems that RDRAM is no better off as far as pin count goes.

However, if we do that, then the whole discussion on dual-channel DDR SDRAM is excluded from consideration, as it is not available today, nor on any roadmaps.

<A HREF="http://freespace.virgin.net/m.warner/RoadmapQ102.htm" target="_new">http://freespace.virgin.net/m.warner/RoadmapQ102.htm</A>

ServerWorks Grand Champion GC-HE Foster MP chipset is expected to be released in January. Grand Champion may well be the first chipset available for the Multi Processor version of Foster (Foster MP)and is expected to support up to 4 Xeon processors, 32Gb of DDR SDRAM memory and PCI-X. The Grand Champion's memory controller features support for 4-way interleaved PC1600 DDR SDRAM (PC1600 is used to keep memory access synchronous with the quad-pumped 100Mhz FSB). This gives the Grand Champion 6.4GB/s of memory bandwidth (100 x 2 x 8 (64bit) x 4) - enough to keep 4 bandwidth-hungry Xeon's happy.

ServerWorks Grand Champion GC-LE Foster chipset is expected to be released in January. GC-LE is the cut down version of Serverwork's GC-HE chipset, designed for use in 2-way Foster SMP environments. The memory controller supports 2-way interleaved PC1600 DDR SDRAM, giving a memory bandwidth of 3.2GB/s.

Rather old news, granted. And rather late (the "January" referred to is <b>this month,</b> which is all but over). But apparently it is on a roadmap somewhere.

Plus, we've seen nVidia do it (though the Athlon can't use all that bandwidth). nVidia would probably do it for the Pentium IV as well, but Intel won't let them for some reason. Perhaps you could enlighten us as to why?

<i>If a server crashes in a server farm and no one pings it, does it still cost four figures to fix?

 

[bront]

There is a fundimental difference between the speed increase in RDRAM vs SDRAM. SDRam vs DDR SDRam is simply double pumping the memory, while the RDR Ram is actualy changing the speed of the FSB. If you want to make a fair compairison, you should compair the latancy of PC800 to PC 1066 to the latancy of PC1600 to PC2100, or perhaps PC2100 to PC2700 (when supported by a CPU)

RAM Disk is not an instalation step.

 

[Raystonn]

One interesting detail that no one seems to have mentioned is that while the theoretical pin count should be different between RIMMs and DDR DIMMs, they are both listed as 184-pin parts.

Some of the pins are entirely unused. Some of them are used to connect to the next RIMM module. (They are serial.)

http://freespace.virgin.net/m.warner/RoadmapQ102.htm

Thanks. I had not noticed that one. I tend to look only at the desktop chipsets/motherboards. This one is designed for the Itanium and Xeon only. It will not be available for the Pentium 4.

-Raystonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =

 

[Kelledin]

It still doesn't really tell us why Intel won't let nVidia do it for the Pentium IV. nVidia's done it in a mere four layers of PCB, so clearly the pin count's not such a serious problem that good engineering can't overcome it.

It sounds as if either Intel is punishing nVidia for supporting AMD, or Intel is going out of their way to make sure DDR never catches up with RDRAM. Neither explanation makes Intel look good, but those are the two explanations that spring readily to mind.

<i>If a server crashes in a server farm and no one pings it, does it still cost four figures to fix?

 

[Matisaro]

Are you going to comment on the other things I mentioned, or do you write an elaborite thread debating one of my non important points instead of focusing on the data which proves your entire claim false?

"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!

 

[Raystonn]

About which things in particular did you want my response? Please keep in mind that I am usually less motivated to respond to those who seem to be yelling and screaming at me, regardless of the content.

-Raytonn


= The views stated herein are my personal views, and not necessarily the views of my employer. =

 

[juin]

I forget this the first 128 FSB

http://service.madonion.com/servlet/Index?pageid=/orb/projectcompare&projectType=6&projectId=2310900

 

[Matisaro]

Whatever ray, from what I have seen of your posting, everytime someone calls you out with facts to back it up, you dont reply and dissapear from the forum.

I didint yell at you, and I didnt insult you, but I brought latency proof to counter every claim you made, most importantly the pc1600 should have less latency than pc100sdram, and that its transistors are working at 200mhz.

And the scaling of latency which exactly follows rdram when you increase clockspeed and not ddr bandwidth like you incorrectly did.

But I dont expect you to reply, because I proved you wrong, and you dont like that, so ignore the post, thats fine. Anyone who can read this thread can see you were wrong, and the links I provided proved it.


If you dont reply to people who seem to be yelling at you, why did you reply to the only one of my points which had a flaw, given your logic you would not have replied at all, so you know what. I dont care if you reply, you know alot, thats for sure, probably all about rambus and intel soultions, but your knowledge on ddr and other systems frankly sucks, and when shown you run away.

Go ahead, if you want to prove my facts wrong, shoot, but try to read my posts before you do so, instead of ignoring those who say you are wrong like you usually do.

"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!

 

[Matisaro]

If we restrict the discussion to what is available today, then we only get 16 pins per memory module. However, if we do that, then the whole discussion on dual-channel DDR SDRAM is excluded from consideration, as it is not available today, nor on any roadmaps.

Nforce is a dual channel ddr solution, and it decreases latency in ddrram systems. Or did you forget that?

"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!

 

[Matisaro]

So rayyston dosent get lost I will post the specific Posts he made and my counterposts so he can concentrate on the debate.


Raystonn says

Sure it is. The memory itself is operating at a frequency of 200MHz. The interface (bus) from the memory to the chipset's memory controller is operating at 100MHz, but transmitting twice per clock. If DDR is only marginally better than SDR in terms of latency, then QDR would be only marginally better than DDR in terms of latency. Latency would really be hurting it. Meanwhile RDRAM is scaling up using frequency...

I replied
"A: ddr sdram does NOT run internally at 200mhz, it merely sends data on the rising and falling edge of the clock, the internal transistor speeds are the same as in pc100 and pc133. Your assertion that latency decreases as you increase bandwidth is wrong, it decreases are you increase CLOCK SPEED. This is supported by this article and quote."

The post above lists the quotes and articles I used to PROVE this statement, the post below that also has links which further prove that statement.



Raystonn said

I would be willing to do that if someone could find a single set of numbers for both PC100 and PC133 or for both PC2100 and PC1600. Thusfar I have not seen anything like this.

To which I replied with this.
<A HREF="http://www.hardocp.com/articles/memory/ddrovr/index3.html" target="_new">http://www.hardocp.com/articles/memory/ddrovr/index3.html</A>

Which is a table showing those results and demonstrating that latcney DOES in fact decrease just like he said they should(as clockspeed increases). However, he claims that a 100% bandwith increase nets 11% reduction in latency, he is comparing across platforms, and he defended this claiming that ddr is 2x as fast clockspeed wise as sdram, which above I proved wrong.

In reality an increase of only 33% (pc100-133) nets a latency reduction of 25%. There as I stated above, no reason no to believe that this would not be the same for a ddr system. Things which go against what raystonn has said.

Clear enough ray, there are other challenges to your claims in the above post, but these 2 are the largest ones, ignore them if you wish, I dont care.


"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!

 

[Matisaro]

Raystonn has so much time to INSULT me in another thread about my oppinion, but no time to defend his bogus statements in this thread even after I pointed them out for him, BUMP, perhaps he missed it, time will tell.

"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!

 

[AMD_Man]

I agree with you there Matisaro. Raystonn seems illogical here. Why would one compare SDRAM RAM to DDR RAM and then RDRAM to higher clocked RDRAM? That's just not a fair comparison. DDR RAM was never meant to improve latency at the same clock speed as SDRAM, although it does seems to somewhat. DDR RAM was designed to do exactly what its name suggests, double the bandwidth. I'd really like a comparison of PC2700 and PC3000/PC3200 when overclocked to PC1066 RDRAM. DDR RAM still wins when you raise the clock speed.

AMD technology + Intel technology = Intel/AMD Pentathlon IV; the <b>ULTIMATE</b> PC processor

 

[Matisaro]

And ddr's latency decreases as clock speed does, and if even pc2100 has lower latency than rdram1066, pc2700's latency will be even lower.


"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!

 

[charliec2uk]

That company was S3. Why they had one I don't know. I think Goldmans handled the aquistion.

Never spit into the wind. Never eat yellow snow.

 

[Copenhagen]

Raystonn has realized that he's wrong here, he doesn't like it, and this is his way of coping with it, that's all.


<i>/Copenhagen</i>

<b><i>Seagate Barracuda IV.
Bad performance in RAID setups!
</i></b>

 

[Matisaro]

Thats what I figure, I really dont want to flame or attack ray, but it really pissed me off that I said something about the nw and retailers in another thread, and ray accused me of fud spreading.
Then when I point out he is wrong and prove it, he refuses to answer and hints its because of my tone, and yet, in the other thread my tone was highly negative(because I was angry), and he replied, because he felt he was right. IN this thread, my tone is not angry, and he refuses to reply to the facts I present.


Just hypocritical IMO.



"The Cash Left In My Pocket,The BEST Benchmark"
No Overclock+stock hsf=GOOD!