Papermaster: AMD's 3rd-Gen Ryzen Core Complex Design Won’t Require New Optimizations

Gillerer

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Sep 23, 2013
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Hint: PCIe *is* I/O.

I can think of at least two reasons why they didn't specify "PCIe" instead of the more generic "I/O":

1) There is also other I/O in addition to PCIe: earlier Ryzen processors had on-CPU USB and SATA, for instance;

2) The lanes can operate flexibly in either PCIe or Infinity Fabric mode (1st gen EPYC on dual-socket systems used half the PCIe lanes in IF mode to connect the CPUs and half were left in PCIe mode). Maybe AMD has some plans to expand on the Infinity Fabric usage beyond dual-socket and intra-CPU?
 

redgarl

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So they can buy the competition (Intel/Nvidia) at a lower price?

No, I want the better product to sell, end of story, and we know which one is going to be the best product.

Things like MSI CEO interview is disturbing at best and I fear that Intel is going back to their good old tactics of buying OEM and blocking the superior product until an anti-competitive lawsuit surface which is going to last 10 years while the damage will be done.
 

redgarl

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Multi-GPU for compute and ML. Mentioned a long time ago.
 

Gillerer

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I should have prefaced "...Infinity Fabric usage" with "CPU...", since that's what I meant - and was talking about.
 

shabbo

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AMD's Heterogeneous System Architecture. Dr. Su mentioned that this was going to play a key role in 2019 and beyond. GPUs need direct access to system memory and CPUs mem-controllers have to be in sync with the GPU's. The result is the CPUs dont have to do all the read/write memory allocations for the GPU thus removing a critical bottleneck. Intel will most certainly go this route once they have a GPU to lock-in users. AMD will take the open-architecture approach given that Ryzen and Vega already support HSA today in ROCm. Nvidia supports it with Power9 IBM servers.
 

Olle P

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No, they told us that the I/O for Rome is 14nm.
The Matisse (Ryzen) I/O is different ("optimised for desktop computers"), with previous rumors suggesting 7nm, and process not mentioned by AMD, hence my question.

 

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