News Quad-Layer 3D Stacking Technology Enables Chips of the Future

[Admin]

A team of researchers with the Institute of Microelectronics have developed technology that enables up to four layers of semiconductor circuitry to be stacked.

Quad-Layer 3D Stacking Technology Enables Chips of the Future : Read more

 

[Kamen Rider Blade]

What happens if you have cooling on both sides of the PCB / Direct Die contact?

Would that help?

 

[Deleted member 431422]

I imagine the internal cooling will be closed loop with heat exchange pipes under cooler. It's going to make the CPU fragile. I wonder how will it be secured from accidental damage.

 

[drajitsh]

Could you please add a clarification as to how this will is different from HBM --as the HBM 1 in Fiji in 2015 had 4-hi memory+buffer logic+ interposer
https://www.tomshardware.com/news/amd-high-bandwidth-memory,29116.html

 

[hotaru.hino]

Could you please add a clarification as to how this will is different from HBM --as the HBM 1 in Fiji in 2015 had 4-hi memory+buffer logic+ interposer
https://www.tomshardware.com/news/amd-high-bandwidth-memory,29116.html

It's probably no different, maybe with the exception of one or two minor details.

This type of IC manufacturing has been around for a while too: https://www.researchgate.net/publication/271453642_3D_ICs_in_the_real_world

 

[TJ Hooker]

And memory layering works very, very differently from logic layering.

Can you elaborate on how memory stacking is fundamentally different than logic stacking?

 

[TanjB]

Looks just like 3Dincites' DBI from years ago, including the F2F - B2B alternation.

 

[drajitsh]

It's different because we're talking about four active silicon dies (that can be logic, SRAM, four Zen 3 dies, etc) being sandwiched together and connected directly via TSVs. An interposer isn't an active computing element (it's just a communications layer), so it doesn't count as one of these layers. And memory layering works very, very differently from logic layering.





The news here is that never before had a four-layer chip was actually manufactured.

4 Zen or any compute dies attached on each other seems more of a technology demonstrator and any real world use, given thermal limits