News Rumor: AMD's EPYC Milan-X CPU to Have 3D Die Stacking

[Admin]

Hardware leakers ExecutableFix and Patrick Schur take turns revealing details about AMD's forthcoming Milan-X processor.

Rumor: AMD's EPYC Milan-X CPU to Have 3D Die Stacking : Read more

 

[Kamen Rider Blade]

I wouldn't be surprised if there is a L4 HBM cache at the bottom with L2/L3 Basement Caches in between with the CCD's at the top.

 

[jimmysmitty]

I wouldn't be surprised if there is a L4 HBM cache at the bottom with L2/L3 Basement Caches in between with the CCD's at the top.

Doubt the CCDs will be stacked in any way yet. More likely memory and maybe I/O. Intel has been working on 3D stacking for a long time and cooling is a major issue to overcome.

 

[Kamen Rider Blade]

Doubt the CCDs will be stacked in any way yet. More likely memory and maybe I/O. Intel has been working on 3D stacking for a long time and cooling is a major issue to overcome.

That could work too, the Central I/O die has some extra thermal capacity =D and space for L4 cache.

 

[thGe17]

Most likely this is simply HBM2-memory on the CPU package substrate ... the same already known for Sapphire Rapids SP to be the case, which seems to have up to 64 GiB directly on the package, speeding up AI-workloads and working as a large L4.
In this case, X3D is according to 3D more something like marketing and does not directly compete with Intels Foveros.

Stacking compute tiles with Milan-X on the other hand is currently highly unlikely because of thermals.