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(emphasis mine)Essentially, the amount of L3 cache remains the same at 32MB per CCD on Zen 3 as on Zen 2. On Zen 2, the four cores inside each CCX only have direct access to 16MB of L3 cache whereas on Zen 3, all eight cores within the CCX share the same 32MB of L3 cache. The revamped design should lower latency substantially and improve overall instruction per cycle (IPC) on Zen 3 parts.
Well, when you do an IPC evaluation, the increased effective local cache size, reduced average latency and any other platform changes also get baked into the IPC figure - uncore improvements improve IPC by letting cores waste less time waiting for stuff.Hmm. Less latency coupled with more IPC will be very helpful to performance.
Yeah, this confidential document leak seems pretty boring as far as confidential document leaks go. I didn't see anything that wasn't already known, or at least rumored months ago. The only thing it really seems to verify is that they are moving to a single 8-core CCX per chiplet, but that was already expected for quite some time.IOW, new details are that there are no new details.
Consider that most of the CPUs sold are Ryzen 3, 5 or 7.It's not just direct access; On Zen 2, the only L3 cache each core has access to is the 16MB residing in the same CCX.
That means that the latency implications should be slightly less than presented in this article: Even now there is never cross-CCX cache access, so the improvement comes solely from more accessible L3 ...
I see your point. I guess I got hung up on the latency improvements presented right after L3 cache change, which gave the impression that that was the main reason for improvements.Consider that most of the CPUs sold are Ryzen 3, 5 or 7.
With Zen 2 these have the L3 cache divided between two CCX s and with Zen 3 all cores have direct access to all L3. Any cross-CCX latency will only affect the few Ryzen 9 sold.