News Samsung Expects Huge Chip Performance Gains From Backside Power Delivery

So many benefits, but what are the drawbacks? Why hasn't this been implemented long ago?
In other articles discussing it, particularly Intel's version (called PowerVia), they detail a large number of technical challenges you have to master.

"Processing a wafer with chips featuring Intel's PowerVia BS PDN involves producing all the complex logic layers as well as signal wires, then flipping the wafer and building the power delivery network 'on top' of the logic. On paper, such a 'flip' does not look like a big deal. However, it adds quite a number of process steps, including removal of 'excess' silicon from the wafer to build the PDN on top of the logic transistors, CMP clean, metrology, lithography, and etching, to name a few."

Source: https://www.tomshardware.com/news/intel-details-powervia-backside-power-delivery-network

I gather backside power delivery is the type of technique that provides greater benefits, the smaller a node you're on. I get the impression that the wires carrying power stopped shrinking a while ago. So, now, they take a disproportionately larger % of real estate, compared to how much they occupied on earlier, larger nodes.
 
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