Semiconductor Production 101

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Good info for someone trying to decide if they want to go into the semiconduction business.Or for someone just lloking to enhance their knowledge a bit.
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It really depends on where you live or want to live with the Semiconductor industry. The pay is great but can be very volatile with the industry in the US. Not a whole lot being built in the US anymore. Most is going to Asia. Even TI is eventually moving all of their manufacturing to Asia.

Something else to consider is if you want to work for a Vendor or manufacturing house. All have their +/-. I have done both and currently work the Vendor side.

Sub
 
I think the article should have touched on what it means when someone says going from xxnm to xxnm...

its referring to the transistor gate distance.
http://jjap.ipap.jp/link?JJAP/40/7077/
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Some do the trench and via in one shot, reducing the steps required

Sub
 
Nice article... It could have been a little more detailed but i still enjoyed reading it.

How about an article about case study (let's say Core 2 Duo) with more details and costs/step involved?

in that way we could make ourselves an idea of the investment made by AMD & Intel into manufacturing...

Paul
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You will have to wait a few generations after the Core2 (65nm) because Intel keeps their manufacutring process and process yields, that gives them their competitive advantage very secret. It is very cool stuff and very impressive, though, especially the new 45nm process. :wink:

AMD can be more open because they have some joint Fabs and joint process development with IBM, and are a Process generation behind Intel.
 
Interesting article that's very appropros for Tom's HArdware. Personally, I'd rather go to an auto magazine for auto articles, but that's just me.

Anyway, here's a question I've yet to get answered. Intel / AMD / IBM / whomever create a brand new chip. So, how do they know it will work as planned? How do they get the basic chip code to work if the chip never existed before?

Let's go back in time. Intel creates the 8008. Who wrote the code that made the chip work without first seeing a working chip? Sort of a catch-22 in my opinion.
 
You would have to work iteratively up to the point where you make a chip like the 8008. Production, especially of high-tech components, is always a matter of adding a little bit of new technology or new processes each new product. In that way, over 20 years of development, you get pretty sophisticated production techniques and corresponding products.
 
Interesting article that's very appropros for Tom's HArdware. Personally, I'd rather go to an auto magazine for auto articles, but that's just me.

Anyway, here's a question I've yet to get answered. Intel / AMD / IBM / whomever create a brand new chip. So, how do they know it will work as planned? How do they get the basic chip code to work if the chip never existed before?

Let's go back in time. Intel creates the 8008. Who wrote the code that made the chip work without first seeing a working chip? Sort of a catch-22 in my opinion.
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So the deal works like that: as we are now pretty much late in the CPU making/designing game, there are lots of capabilities. But in general you just ask yourself - what is CPU? The answer: it is piece of code and some kind of instructions embedded in silicon. So what you can do is you can simulate on PC how this piece of code will work, add some instructions, delete them, optimize them etc. while it is a software. I don't know how they debugged 8008 microcode, but it can be something similar.

Then there is a step of translating code into electrical scheme, meaning that you have to implement all these instructions in terms of logical elements made out of transistors etc. Here some elements have to be added because of the simple fact that microcode knows nothing about real life and electricity so some complementary circuitry (such as capacitors, electro-static discharge diodes, power pumps etc.) is added

Then, knowing what will be the technology used for the CPU manufacturing, electrical scheme is tranfered to physical layout of layers of semiconductors, conductors and insulators.

The question is - how you debug these steps. Usually designers have some simulation tools and there are companies, which make pretty cushy living out of selling verification software.

But nothing is finally proved until the design meets production fab and real silicon chip is manufactured. Then there are testers, which run specila tests on CPUs and according to the chip's response desision is made if everything is operating properly.

If yes - we are good and here you have your brand new shiny C2D/Athlon or whatever.

If not - see my comments on revisions and steppings. So it is pretty much iterrative process until all the bugs are adrressed.

Enjoy,

CousinVinnie
 
If I am correct with the FAB, Fab 22 only has 4 LRC etchers for PAD Etch. The very end of the process. I hate those damned tools. TEL and Hitachi do all those dry etching for the front and back end. STI, Poly, HM, Spacer, Contact, Via, Trench, Nitride. That is for 130nm, 65 and 45nm are Top Secret, and radically different.
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Those tools (Rainbows) are at least 10 years old and yes, they are a PITA. The new 2300's are way easier to work on and safer too.
 
Nice article which would have been a better read if someone had proof read and edited the copy 🙁


Where is the quality?

You know two things I would like to have, just because I'm a geek, is a polished 200mm or 300mm wafer and a whole mono-crystal :)
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I've got a couple of samples of both hanging in my office; I think just about everyone in the industry does. (Well, the geeks among us :) )

You can buy them online I believe; used ones are not that expensive for some interesting wall art... just make sure you get insurance on the shipping :) :) :)
 
And of course they completely leave out Metrology ;-)

SOG is normally used as a dielectric for insulation between metal layers...
The article quoted above is just a work around solution where they use the SOG as a protectant against the etch process... a sacrificial layer.

When SOG is used as a dielectic between metal layers it could be compared to the rubber insulation between two wires in a cable...
The rubber insulation on a wafer would be the SOG.
Typical chemistry for dielectric layering is TEOS or Silane. (doped or non doped)

P.S. For those interested in the picture for wire bonding.... those pics come from the SEM equipment. Metrology equipment.
Without metrology there isn't any FAB... :roll:
 
One note to the previous post: 90nm P4 parts never been manufactured in Israel (or any other 200mm factory of Intel).

CousinVinnie
 
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