I think you made a wrong assumption: the 2 512MB modules have to be mounted on the same channel, making a total of 1GB on one channel, equals to the single 1GB module mounted on the other channel.
Let you have a 4 slot mobo: 0 & 1 on CH0, 2 & 3 on CH1.
If you put two 512MB modules on slots 0 & 1 they'll use the 64bit bus of CH0 and will be addressed in sequence (there are dedicated address decoders on RAM controllers that do this): they will be concatenated in a unique contigous array of 1GB.
This is how *ANY* memory bus works, not only the PC ones.
The two channels are 64 bit each, no matters how many modules you put in the slots. Obviously the BIOS FW must be able to program the address decoders in the right way in order to access the modules in the correct way: the majority of them (like Via) will disable dual channel operation if they found different number of modules per channel, regardless of their size.
And there is an explanation for this: the very first DDR mobos only had 3 slots, because of problems in PCB traces and bus drivers that did not garantee signals integrity with 4 slots. With theese mobos you could only use 2 modules in dual channel or 3 in single channel, because of trace delays problems.
Many BIOSes are still inherited from this old stuff, thus not allowing the 3 modules configuration.
As I said many times, it is only related to the BIOS FW ability to correctly recognize the RAM configuration and properly program the RAM controller and this is not an easy issue: SPD data aren't standard at all and many SPD chips contain wrong parameters (as reported in many articles by TomsHardware itself!) and this is why, in our image processing system boards, we often reprogram the SPD chip with new correct values.