IntelEnthusiast :
Part of the problem with your question is that because of the integration of the memory on the processor; you have to have a processor that support ECC memory. The easiest way that you are going to get support for ECC in Socket 1155 is to use the Intel® S1200BTS which is a micro-ATX board that will support our Intel Xeon® E3-12XX processors and some Intel Core i3 processors. You can see a list of the supported processors on this board at
http://ark.intel.com/products/53558/Intel-Server-Board-S1200BTS and additional information on the board.
Christian Wood
Intel Enthusiast
There are a myraid of methods for implementing ECC.
1. Within the dynamic refresh memory chip itself. But with no method of detecting correction failures.
2. With motherboard hardware and totally independent of X86. Again, no method of detecting correction failures.
3. Totally on the motherboard but with # of ECC corrections done and reportable via X86 processor interrupt/BIOS. Failed correction also handled via X86 interrupt/BIOS.
4. Partially on the motherboard
a.) Writing of ECC memory extension contents computed via motherboard hardware.
b.) Memory read checking of need for ECC correction detected by motherboard hardware.
c.) Via interrupt/BIOS, X86 processor computes and corrects memory cell contents
d.) Correction failure handled by X86 BIOS.
1, 2, Would still provide substandually improved system reliability, robustness, over non-ECC memories since non-correctable base memory contents would be rare in the extreme in comparison.
Obviously #3 would be the most desireable for server and certain so for mission critical applications such as is Strobe Data's PC Co-processor product series.
It would be my guess that the Xeon class, LGA-1155 for instance, motherboards make use of #3 and the X86 is only interrupted if the correction fails.
Can Christian Wood enlighten us?