News TeamGroup Unveils 120mm AIO Liquid Cooler For PCIe 5.0 SSDs

I wish OEMs to revive the modular quick disconnect AIOs like fractal and Alphacool models they once had. Having the option to integrate the SSD cooling is much more elegant than have a dedicated AIO wasting space and money...
 
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I'm so happy to have a PCIe 4.0 SSD that will last me a very long time. These 5.0 SSDs needing active cooling look like too much trouble for the extra performance. I mean, a dedicated AIO for just one SSD? A copper tower? Feels like overkill, or underdeveloped SSD tech.
 
Actually they nailed the gimmick i have to admit, maybe a bit pricey, but many people have an exhaust fan there, and some will like the idea of "killing two birds with one stone" here.
 
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Give it a generation or two for PCIe controller designers to optimize the PHYs and the rest of the controller to also get power-optimized for that amount of bandwidth, then we'll be back to simple heat-spreaders being more than good enough again.
 
Give it a generation or two for PCIe controller designers to optimize the PHYs and the rest of the controller to also get power-optimized for that amount of bandwidth, then we'll be back to simple heat-spreaders being more than good enough again.
I expect PCIe 5.0 is always going to have a significant power increase over PCIe 4.0.
 
I expect PCIe 5.0 is always going to have a significant power increase over PCIe 4.0.
While they may never reach power-efficiency parity with 4.0 controllers, I'm sure they can close the gap quite a bit just like how 4.0 closed most of the gap with 3.0 after 3-4 generations mainly because manufacturers quit releasing new, more power-efficient 3.0 controllers.
 
While they may never reach power-efficiency parity with 4.0 controllers, I'm sure they can close the gap quite a bit just like how 4.0 closed most of the gap with 3.0 after 3-4 generations mainly because manufacturers quit releasing new, more power-efficient 3.0 controllers.
Isn't there a fundamental increase in power needed to drive the interconnect at such high frequencies? Newer process nodes aren't going to fix that, not least because I think I/Os tend not scale down well.
 
Isn't there a fundamental increase in power needed to drive the interconnect at such high frequencies? Newer process nodes aren't going to fix that, not least because I think I/Os tend not scale down well.
The analog parts don't scale well - junctions able to pass 5-20mA can only ever be so small, much the same for anything with critical accuracy in the differential receiver and transmitter circuit.

One way I could imagine engineers reducing out-to-in power is by eliminating termination networks: if you model the transmission lines accurately enough, you could shape driver outputs to only use enough energy to morph the standing wave from one state to the next instead of dumping all of the energy into termination, which could save almost half of the bus power.