Temperature Sensor Help

[willi1615]

Hello, I recently just built my first system and everything has been working great so far. But I have some concerns over the temperature sensors. I have read the guide on core 2 temp sensors but my sensors seem to be confusing me.

System:

Motherboard = Gigabyte EP43-UD3L
CPU = E7400
Stepping = R0
CPU Cooler= XIGMATEK HDT-S1283
Case = Antec 300 with stock fans on low
Ambient = ~17C

Frequency = 3.8 Ghz (400x9.5)
Vcore Load = 1.248 (by cpu-z)

Load = Prime95 - In-place Large FFTs
Tcase (Temp3 by Speedfan) = 22c Idle, 62c Load
Tjunction0 (Core0 by Speedfan) = 36c Idle, 42c Load
Tjunction1 (Core1 by Speedfan) = 41c Idle, 42c Load

Load = Prime95 - Small FFTs
Tcase (Temp3 by Speedfan) = 22c Idle, 50c Load
Tjunction0 (Core0 by Speedfan) = 36c Idle, 45c Load
Tjunction1 (Core1 by Speedfan) = 41c Idle, 45c Load

The core temperatures are really confusing me. I read that some core duo's stick at low temps but shouldn't they be ~5C higher than Tcase at full load? RealTemp reads the same core values as well.

From what I understood out of the temp guide you can calibrate them by adding an offset which is based off of Tcase. Doesn't really make sense to me to just add a value to them to make them read 5 higher then Tcase, when you can just look at Tcase only. But I think I am getting that part messed up.

Any help with this would be greatly appreciated, and is 62C too high for that one reading?

 

[RJR]

Speedfan, not one of the most reliable for temps. In your case the Tcase 22c idle and cores at 36-41c idle, does that seem like it would even be possible.

CoreTemp or RealTemp and core temps below 70c and your fine. Intel thermal spec 74.1c

 

[willi1615]

RealTemp and CoreTemp both read the exact same temperatures as Speedfan.

 

[RJR]

Nobody likes doing things the easy way anymore, OK.

I don't remember seeing a sensor in the middle of my processor's case when i've installed them, how about you? It would make it hard to mount your heat sink with a sensor there. And no there isn't one in the TIM below the processors IHS.

 

[randomizer]

Speedfan, not one of the most reliable for temps.

It reads the same data as all other programs. How then is it less reliable?

In your case the Tcase 22c idle and cores at 36-41c idle, does that seem like it would even be possible.

Without calibration nothing is impossible. My CPU is a prime example of the impossible being reality.

CoreTemp or RealTemp and core temps below 70c and your fine. Intel thermal spec 74.1c

The Intel Thermal Spec. doesn't relate to core temps, but it is a good idea to keep core temps below it for longevity purposes regardless. Have you read the Temp Guide yourself?


Also, I really can't see how that last post of yours relates to his thread. So you posted a couple of images, and...?

 

[RJR]

Without calibration nothing is impossible. My CPU is a prime example of the impossible being reality.

How do you calibrate something that has NO sensor? The software just guesses the temps.

The Intel Thermal Spec. doesn't relate to core temps, but it is a good idea to keep core temps below it for longevity purposes regardless. Have you read the Temp Guide yourself?

No it relates to Tcase, guess how you get your Tcase temp, see my last post,Dahhh. Thanks for playing.

 

[randomizer]

How do you calibrate something that has NO sensor? The software just guesses the temps.

Ok, so you haven't read the guide. Stop giving advice, you clearly don't understand what you're talking about. Software can't make wild guesses, it isn't human. It needs data to make estimates. Those estimates are usually not correct, but they can be calibrated. Why do you trust Real Temp and Core Temp? They make just as much of a "guess" by your definition.

No it relates to Tcase, guess how you get your Tcase temp, see my last post,Dahhh. Thanks for playing.

It depends on your definition of TCase. Strictly speaking you need to drill a hole in the IHS and insert a thermocouple to read the "real" TCase. However, for all intents and purposes TCase refers to the "CPU" temperature reported by Speedfan (provided it labels this temperature that way). This is not a wild guess, if you've read the Temp Guide or more than one page of Intel's documentation.

Thanks for letting me play.

 

[jsc]

But randomizer, the temperature guide is hard.

 

[randomizer]

I couldn't work out if that was sarcastic or not. I'll assume it wasn't, because it is hard. But if you haven't read it, or you don't understand any of it, you shouldn't be giving any advice on the topic. Blind leading the blind, as they say. I don't claim to understand everything, but I try to correct people when they are flat out wrong about what they are saying.

 

[RJR]

Well, to be honest guys, I've never read it. So after my little anger management moments last night (real bad day) I decided to actually read it today.

To my very simplistic and sometimes logical mind it still leaves me with questions. In my mind stating a 5c gradient between tcase and tjunction with all the different variables involved no matter how many cores are involved just doesn't settle well with me. But seeings I'm unaware of the exact placement of this substrate sensor below the cores that is determining this Tcase temperature and if this sensor is located in a strategically different area to compensate for the number of cores involved (not to mention the exact amount of Tim, IHS makeup, case thickness, etc.) I'll have to take your word for it.

It would be appreciated if someone could reference me a schematic of sensor locations for various chip designs. Thanks.

Oh, almost forgot, after this debate is over determining the validity of the Tcase temperature readings, it will still be a simple fact that keeping your core temperatures below Intel's stated Thermal spec will keep you in good shape thermally.

 

[RJR]

Just found this TH article on Intel's DTS:

http://www.tomshardware.com/news/intel-dts-cpu,6300.html

 

[willi1615]

It seems my core readings get stuck at 36 and 41 when at low temps. I guess mostly what I am wondering is why at load they are lower then the other temperature.

Also what is the difference between Small FFTs and In-place Large FFTs? When I run large FFTs Tcase is much higher but the core temps are lower.

 

[RJR]

Willi, i'll let ramdomizer field your question. I just wanted to apologize for going off on the completely unnecessary rant yesterday. It was completely uncalled for on my part.
I'm sure he will be glad to help you out with your questions.

 

[randomizer]

I was unable to find any decent images showing the precise location of the analog diode (this being fairly poor IMO), but the DTS is actually not a single sensor per core. CompuTronix will be able to elaborate further and more accurately, but my understanding is that multiple "hot spots" around the die have temperature monitoring devices and the highest recorded temperature at a given time is what is reported as the Distance to Tjunction Max for that core. The rest of the core is running cooler, so as long as the hottest point is at a safe temperature the rest will be also.

The 5c offset is a "worst case scenario" once calibrated, because as you can see from this graph the offset can be as low as 0C. This document describes in further detail how they came to get those offsets, but the most important thing is that it changes depending on the type of load. We can't change the offset for all possible load types, so we account for the worst case. If the diode reads 70C and the actual offset is 0C under that load then we will be showing core temps 5C too high. However, under a different load condition we might have the same diode temp of 70C but up to 75C on the cores. If we account for the 5C at all times then we avoid doing damage to the CPU by reading temps lower than they may be. ~5C ends up being pretty average for most applications anyway, and proper calibration using the Guide should reveal temperatures close to those reported by Real Temp at load (although probably not at idle unless you calibrated Real Temp as well). This might not be entirely correct (in fact it almost definitely isn't), as I've been trying to understand this mind-boggling topic myself since August. CompuTronix, as I said earlier, can clarify things more clearly.

The calibration procedure in the Guide exposed some rather interesting thermal characteristics about my particular CPU. It would appear that for whatever reason, Tjunction Max (the actual one for my chip, not what some Intel presentation slides say) is set far too low and my core temps are being reported very high because of this - and throttling early as well. Can't be entirely sure though, not without tearing off the soldered IHS and doing some serious testing with a calibrated IR gun (which I don't have).

Regarding the TH article on the IDF presentation, it's probably a little dated now, as more things have been revealed by Intel (*ahem* sort of) and by the guys at XtremeSystems who have been researching this with real-world testing for a long time. In fact, we recently hit 140 pages in the Real Temp thread there :lol:

 

[toledo_speedo]

Ok willi1615 I am not trying to trivialize any of the preceding posts but an E7400 OC'D TO 3.8gHZ running under load is a joke. There has been some good information listed above, but you are not anywhere near a point where your temps are a factor. You will hit a FSB/CPUx ceiling before you will come close to overheating that CPU.

 

[willi1615]

Yeah I was pretty happy with the 3.8 ghz settings but I wanted to make sure I was reading the temps correctly before I tried to go higher.

 

[RJR]

I was unable to find any decent images showing the precise location of the analog diode (this being fairly poor IMO), but the DTS is actually not a single sensor per core. CompuTronix will be able to elaborate further and more accurately, but my understanding is that multiple "hot spots" around the die have temperature monitoring devices and the highest recorded temperature at a given time is what is reported as the Distance to Tjunction Max for that core. The rest of the core is running cooler, so as long as the hottest point is at a safe temperature the rest will be also.

The 5c offset is a "worst case scenario" once calibrated, because as you can see from this graph the offset can be as low as 0C. This document describes in further detail how they came to get those offsets, but the most important thing is that it changes depending on the type of load. We can't change the offset for all possible load types, so we account for the worst case. If the diode reads 70C and the actual offset is 0C under that load then we will be showing core temps 5C too high. However, under a different load condition we might have the same diode temp of 70C but up to 75C on the cores. If we account for the 5C at all times then we avoid doing damage to the CPU by reading temps lower than they may be. ~5C ends up being pretty average for most applications anyway, and proper calibration using the Guide should reveal temperatures close to those reported by Real Temp at load (although probably not at idle unless you calibrated Real Temp as well). This might not be entirely correct (in fact it almost definitely isn't), as I've been trying to understand this mind-boggling topic myself since August. CompuTronix, as I said earlier, can clarify things more clearly.

The calibration procedure in the Guide exposed some rather interesting thermal characteristics about my particular CPU. It would appear that for whatever reason, Tjunction Max (the actual one for my chip, not what some Intel presentation slides say) is set far too low and my core temps are being reported very high because of this - and throttling early as well. Can't be entirely sure though, not without tearing off the soldered IHS and doing some serious testing with a calibrated IR gun (which I don't have).

Regarding the TH article on the IDF presentation, it's probably a little dated now, as more things have been revealed by Intel (*ahem* sort of) and by the guys at XtremeSystems who have been researching this with real-world testing for a long time. In fact, we recently hit 140 pages in the Real Temp thread there :lol:

Well, this is all well and good but it still seems to me that to obtain an accurate Tcase measurement is beyond the scope of the normal enthusiast at this time. Whether the offset is 0c or 10c or anywhere in between you still have a simple fact that remains: Once the Tjmax is disclosed by Intel, your easiest and most accurate (although not 100%) way to monitor your temps is by using core temperatures and keeping them at or below Intel's Specs. Or if Tjmax is not disclosed a simple distance to Tjmax reading is all you need, since that will not change with your Tjmax setting. Seems pretty easy and logical to me.

 

[randomizer]

Well you need to take my interpretation of the graph I linked with a grain of salt, as I am not an engineer and may not have understood it correctly. I don't like whitepapers much 😉

There is a problem with simply using absolute core temps based purely off Tj Max, or even using distance to Tj Max alone. Intel never disclosed Tj Max exactly, nor could they. They disclosed what they called Tjunction Target. They are in a sense the same thing, except that there is no guarantee that the Tj Max for your CPU, or even the individual cores, is equal to the Tj Target that Intel disclosed for your CPU model. CompuTronix made a very nice post here worth reading: http://www.tomshardware.com/forum/250157-29-q6600-tjmax-right#t1784839

I'll point out the important part for this discussion:

Intel has stated that the DTS sensors are designed for Throttling and Shutdown protection, are more accurate at very high temperatures, become unreliable below 50c, and should be disregarded at Idle. Intel has also stated that Tjunction Max values vary between individual cores, and have a "range" or target value that can be as much as +/- 10c due to variables such as sensor "slope" error, which is especially pronounced on 45nm parts. This highlights the reason why Tjunction Max Values are rounded to the nearest 5c, such as 85c or 100c, while Tcase Max values are instead precise numbers to the tenths of a degree, such as the Q6600 B3 at 62.2c

Now Intel has said that Tjunction Max is subject to error because the DTS is not perfect. In a given CPU family, the DTS has a margin of variation equal to +/- X (Yes, X is what they've told us. Had they given an actual figure things would be more interesting). The following slide gives a graphical explanation:



To save time typing the same thing, here is what Intel told me in an email when I queried them about this slide:

For example, if the Tj Target is 100 C, and let’s say X is 5 C, then the DTS calibration point will be 105 C. Therefore, in this example, the calibration point for all devices will have a range of 2X and the actual temperature of a particular chip will be somewhere between 100 and 110 C.

Therefore we have encountered another problem. The DTS may report temperatures up to 10C too low at Tj Max in this example. This isn't a problem for thermal protection really, but for the temperature paranoid it may be. This is why Tj Target is not a precise value, because the DTS has such a large margin of variation and a precise value would be infeasible. Remember that Tj Max can vary between cores, no just between CPUs. Now Intel hasn't disclosed the margins of variation for each processor stepping so we don't have a solid idea of what it is unless we go testing a large number of CPUs to see when they throttle.

I better end this post here before I digress