News TSMC and SK Hynix team up for HBM4 co-production: Report

[Admin]

TSMC and SK Hynix reportedly join forces to build products for AI, including HBM4 memory.

TSMC and SK Hynix team up for HBM4 co-production: Report : Read more

 

[8086]

This kind of bandwidth is exactly what modern multi-core CPUs need as current two channel bandwidth is often the limiting factor or bottleneck to better performance. And of course, we all know GPUs will likely be the first to adopt this technology.

 

[usertests]

This kind of bandwidth is exactly what modern multi-core CPUs need as current two channel bandwidth is often the limiting factor or bottleneck to better performance. And of course, we all know GPUs will likely be the first to adopt this technology.

And more often than not, enterprise-priced AI cards and GPUs.

CPUs/APUs ultimately need big L4 cache on package/die to remove the DRAM bottleneck.

 

[8086]

And more often than not, enterprise-priced AI cards and GPUs.

CPUs/APUs ultimately need big L4 cache on package/die to remove the DRAM bottleneck.

Intel gave us triple channel ram a decade ago, so why hasn't this become more of a norm? I would happily settle for 3 dimm slots over the current 4.

 

[usertests]

Intel gave us triple channel ram a decade ago, so why hasn't this become more of a norm? I would happily settle for 3 dimm slots over the current 4.

I did not know about triple-channel Nehalem/Westmere. I believe those were considered HEDT parts of their time, replaced with quad-channel Extreme CPUs in subsequent generations.

https://www.anandtech.com/show/3833/intels-core-i7-970-reviewed-slightly-more-affordable-6core

If we see more channels on lower-priced consumer sockets in the future, it will probably be quad-channel. If you want more than dual-channel, you probably want a lot more, particularly for integrated graphics. And that's exactly what we should see with AMD's Strix Halo, which has a 256-bit memory controller.