News TSMC discloses N2 defect density — lower than N3 at the same stage of development

[Admin]

TSMC claims N2 defect density is lower than N3 defect density two quarters before mass production starts, reveals N2 HVM time frame.

TSMC discloses N2 defect density — lower than N3 at the same stage of development : Read more

 

[User of Computers]

this isn't particularly surprising, N3 yields at launch weren't amazing

 

[usertests]

Everyone be hating on N3, but it's going to stick around for the next 10-20 years as the last TSMC FinFET node, so they can fix it up gradually.

 

[thestryker]

Everyone be hating on N3, but it's going to stick around for the next 10-20 years as the last TSMC FinFET node, so they can fix it up gradually.

I don't think it was bad by any means, but they'd gotten too aggressive with SRAM scaling which caused yield issues with the first version. It's still a good node (and I'm sure all of the derivatives after N3E will be great) aside from clock scaling, but that seems to be an issue with TSMC's nodes in general.

 

[Gururu]

Let us see some performance on test silicon already.

 

[dalek1234]

So TSMC discloses n2 defects density when compared to previous node, which Intel hides theirs. Got it.

 

[abufrejoval]

So TSMC discloses n2 defects density when compared to previous node, which Intel hides theirs. Got it.

I agree that this seems to be a slightly obfuscated message aimed at decisive people in the know designed to tilt some rather political decisions.

Unfortunately I personally don't have the foggiest as to what this actually means.