News TSMC Dishes on 5nm, 4nm, and 3nm Process Nodes, Introduces 3DFabric Technology

Endymio

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3nm is two full process nodes ahead of 5nm ... and only netting TSMC a 10-15% performance increase? That seems a bit paltry, doesn't it?
 

hannibal

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Well people have to remember that these Numbers Are pure marketing so 3nm is not even same ballpark with real 3nm... so the improvements Are Also smaller . In reality these still Are about 40 to 54 nm in reality...
 

Afrospinach

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From what I understand "3nm" does not necessarily mean what it has traditionally meant and more of a marketing label, perhaps as is mentioned above why the improvements seem underwhelming. 3nm is half the size of 7nm, that is huge. In the past that has meant an almost linear half power consumption.
 

Endymio

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correct me if I am wrong , isnt true 3nm impossible to reach ?
Certainly with current understanding it is (though as previous posters have pointed out, current process nanometer nomenclature is essentially marketing rather than actual physical size). I do recall plenty of stories in the late '90s that anything below 100 nm was essentially impossible. So at some point in the future, we very well may see transistors of 3nm or even smaller ... though quite probably through some process rather than lithography.
 

nofanneeded

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Certainly with current understanding it is (though as previous posters have pointed out, current process nanometer nomenclature is essentially marketing rather than actual physical size). I do recall plenty of stories in the late '90s that anything below 100 nm was essentially impossible. So at some point in the future, we very well may see transistors of 3nm or even smaller ... though quite probably through some process rather than lithography.

I know that scientists made ~0.18nm transistor using 13 atoms around a molecule which is the theoretical limit , and cannot be made into a whole chip ... but I dont know why they say 3nm is the limit actually.
 
.. but I dont know why they say 3nm is the limit actually.
Because you need at least x many atoms to create enough signal and at least y many atoms to make a gate that will keep the electrons from leaking.
With silicon being 0.2nm in size 5 atoms are already 1.2nm and that's what's needed for the gate alone,leaving about another 5 for everything else....
However, with current gate oxides with a thickness of around 1.2 nm (which in silicon is ~5 atoms thick) the quantum mechanical phenomenon of electron tunneling occurs between the gate and channel, leading to increased power consumption.
https://www.kth.se/social/upload/233/MOSFET.pdf
 

jimmysmitty

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"TSMC Possibly Moving Beyond Silicon for Sub-3nm"

This is probably the case as Intel and many other semiconductor companies have already begun researching new materials to replace silicon. Hell they were talking about this way back in 2007:


I also remember reading about possibly using graphene as a replacement:

https://phys.org/news/2014-08-future-fast-chips-graphene-silicon.html

One of us is reading that chart wrong. I read it as mutually exclusive: 10-15% more performance at the same power draw, or 30% less power at the same performance. Not both at once.
This is the most likely case. Most node improvements are one or the other.
 

Mr Marshall

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correct me if I am wrong , isnt true 3nm impossible to reach ?
KAIST developed a 3nm multi-gate in 2006. NEC developed a 3nm channel in 2003. While not as complex as today they showed 14 years ago it was possible. I will never understand why people don't believe it's possible with 15 more years of research or more already laid out.

Going to add that they are indeed 3nm gates as Samsung has stated themselves. Seeing how the Korean Government funded the original research and they are heavily invested in Samsung. There is no surprise they are actually using 3nm gates in the traditional sense.

TSMC already had a break-through this year for 2nm gates. They found that Finfet isn't going to be as reliable below 3nm.
https://finance.technews.tw/2020/07/13/tsmc-2nm-gaa/
 
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Endymio

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TSMC already had a break-through this year for 2nm gates.
TMSC's gates for their N2 process are not 2nm in size. On the order of 6nm will be the best bet.

As for the KAIST research back in '06, they hit 3nm with the fin, but the gate itself was a little larger.
 

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