News TSMC Says a Shortage of Commodity Chips Is Disrupting Trillion-Dollar Industries

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Nice attitude you got there sparky. Here's a clue, you can't get blood from a turnip, and if the temperature outside is 106 in the 2nd largest state in the country (Texas) it's probably 103 in neighboring areas on the grid. If the wind doesn't blow, power generation drops, and the grid can't make up that kind of difference.

The result is that they have to bring reserve generators online. Those reserve generators have to be there, they cost money to put in, and to maintain. About $1B / year in Texas.

But I bet that's not about reality for you now is it? Some kind of agenda?

No agenda, it's just that your propaganda lead post doesn't line up with reality. Since the invention of natural gas powered plants on demand power has been a thing. In fact it has been a thing for almost 30 years. When utilities build out variable rate sources they back it up with on demand resources either with physical plants or buying the energy from neighboring markets (this isn't even accounting for stored energy). It would take a major major issue with either on demand resources, stored energy or neighboring markets for there to be an issue when the "sun" or "wind" sources fail to produce. Also, just in case you're not aware, the odds that you get a day where the sun is blocked by clouds and calm wind are almost zero. For solar not to work due to clouds the clouds need to be very dense, and when clouds are dense, wind blows.
 
That is not true, to use a new node you would had to remake the tooling, so you cant just put a 120nm design to TSMC and ask them to make it on 7nm, you would have to rebuild the chip. This is why you don't get node shrinks very often (proper node shrinks not 7nm to 6nm which is an optimisation).
I didn't say optical shrink 120nm to 7nm. I said that a 1M transistor design requires approximately the same effort to make regardless of what process you make it on, the implication being re-doing the design from scratch or at the very least re-do it from layout, not optical shrink an existing design.
 
I didn't say optical shrink 120nm to 7nm. I said that a 1M transistor design requires approximately the same effort to make regardless of what process you make it on, the implication being re-doing the design from scratch or at the very least re-do it from layout, not optical shrink an existing design.
I am sorry I don't understand your point then. You were claiming that 32nm machines could easily print 120nm designs with little to no effort, no one said that they would have to do all the R+D again but there is still a heavy cost retooling your design for a newer node regardless if you make any architectural changes. As I stated before as well your chip would not perform the same on a newer node as it does on an older node meaning that again you would have the costs testing and revalidating everything.
 
You were claiming that 32nm machines could easily print 120nm designs with little to no effort, no one said that they would have to do all the R+D again but there is still a heavy cost retooling your design for a newer node regardless if you make any architectural changes.
If you make a 120nm chip on a 32nm process based on the same light source still at 120nm size, you could hypothetically re-use existing 120nm masks since you don't need any of 32nm's resolution enhancement steps.

You need a re-design when shrinking a chip because it changes trace lengths for PLLs, DLLs, clock trees, etc. You don't have that problem when leaving all dimensions as-is, just using equipment capable of higher resolution you aren't using.