News TSMC shares deep-dive details about its cutting edge 2nm process node at IEDM 2024 — 35 percent less power, or 15% more performance

If I'm not mistaken, NanoFlex/FinFlex can allow you to have multiple types of cells on a single chip, so you could optimize for P-cores and E-cores in the same monolithic design for example.

There may be no free lunch anymore but these are good efficiency gains, and SRAM scaling isn't quite dead yet.

Looks impressive. I wonder how many years will pass before any chips baked with this hit the consumer market.
They should appear in 2026.
 
I always found it a little hard to believe that backside power gives Intel such an unassailable advantage that TSMC wouldn't be able to hold court with it. I figured TSMC's N2 nodes are going to pack a lot of improvements, maybe even enough to compensate for that deficit. Perhaps we'll find out, if Intel's 18A doesn't fall too far behind schedule.
 
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Yea, there's some smart people in this world. How is 2nm even possible! I mean, I know how they do it with lithography and EUV light and all that, but still, I dont understand how we even figured these things out in the first place. It's incredible.
 
Yea, there's some smart people in this world. How is 2nm even possible! I mean, I know how they do it with lithography and EUV light and all that, but still, I dont understand how we even figured these things out in the first place. It's incredible.
The node names are not actually equivalent to the number they purport.
 
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Yea, there's some smart people in this world. How is 2nm even possible! I mean, I know how they do it with lithography and EUV light and all that, but still, I dont understand how we even figured these things out in the first place. It's incredible.
"2nm" is a marketing name, the names do not necessarily correlate to any feature size anymore.

There are a lot of brains in the operation though. Just look at fab tools.

Business-ASML---Employees-assembling-an-EUV-system-(ASML).jpg
 
I always found it a little hard to believe that backside power gives Intel such an unassailable advantage that TSMC wouldn't be able to hold court with it. I figured TSMC's N2 nodes are going to pack a lot of improvements, maybe even enough to compensate for that deficit. Perhaps we'll find out, if Intel's 18A doesn't fall too far behind schedule.
Intel damage control is out in full force for 18A. They even got the fired CEO to defend it, incredible.

https://www.tomshardware.com/news/tsmc-our-3nm-node-comparable-to-intels-18nm-tech

We've seen the backside and forth on 18A and N2. 18A's schedule will slip and won't be much better (if at all) than N2. TSMC will respond in an orderly fashion with A16 with backside power and that will be that.
 
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If I'm not mistaken, NanoFlex/FinFlex can allow you to have multiple types of cells on a single chip, so you could optimize for P-cores and E-cores in the same monolithic design for example.

There may be no free lunch anymore but these are good efficiency gains, and SRAM scaling isn't quite dead yet.


They should appear in 2026.
After Panther Lake or Nova Lake there will be no P or E cores, it will be one core that can be freely clocked to serve any role as required performance or efficiency etc.. Rentable units are coming.
 
After Panther Lake or Nova Lake there will be no P or E cores, it will be one core that can be freely clocked to serve any role as required performance or efficiency etc.. Rentable units are coming.
I say it generally. Could apply to Intel, AMD's regular + 'C' cores, or ARM (the TSMC chart shows Cortex-A715).

Also, it should be pointed out that Intel's plans are in extreme flux, rentable units / Royal Core might not be coming, and they just ditched a CEO. Who knows what their E-core plans are anymore? Especially 3+ years out.
 
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