Unnanounced AMD Threadripper 1920 Listed, Other Non-X Models Likely To Follow

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Three interleaved channels still enable the memory controller to service three concurrent memory accesses to different addresses when the addresses hit different memory channels, which should happen fairly regularly on a CPU running multiple threads.
 


Well unless something changed in x299 skylake-x cpus from x79 and x99 cpus that im not aware of, they all had support for proper triple channel while supporting quad channel as well.

 

Did you mean non-interleaved? Do you know they operate independently and concurrently, or are you just speculating?
 

It's ironic that this thread started with a post about fact-checking.

I have an X79-based board and neither the motherboard documentation nor the information from Intel about memory speeds in different configurations said anything about triple-channel configurations. This subject has come up before, and I didn't find anything from Intel saying that X79 or X99 ever supported triple-channel. Can you find a single piece of official documentation from Intel that either 3-way interleave is supported? Can you find anything showing that populating 3 of the memory channels of X79, X99, or X299 ever significantly out-performs a single-channel config?
 


Well dont know which motherboard you have and dont know why it's not listed but i can find pretty quickly motherboard manuals mentioning triple-channel support on both x79 and x99.

X79 https://www.gigabyte.com/Motherboard/GA-X79-UD3-rev-10#support-manual
X79 https://www.intel.com/content/dam/support/us/en/documents/motherboards/desktop/dx79to/dx79to_productguide01_english.pdf

X99 https://us.msi.com/Motherboard/support/X99S-SLI-PLUS.html#down-manual

and for that second x79 link, that intel board (dx79to) specifically mentions

• Support for single-channel configurations and dual-, tri-, and quad-channel memory interleaving

Beyond that, intel is pretty light on info about channel interleaving... Only really mentioned in this article for the skylake architecture on how memory is accessed.

https://software.intel.com/en-us/articles/how-memory-is-accessed

Intel® microarchitecture code named Skylake supports 1, 2, 3, 4, and 6-way interleaving. If five channels are populated, the home agents are probably using a 2-way and a 3-way interleave. 3-way and 6-way interleaving support implies the hardware can do mod 3 calculations on the addresses – a non-trivial amount of work.

Although i haven't read the article fully (too tired to fully comprehend the info at the moment) but im not sure they're talking about ram memory, 3D-Xpoint, or something else completely..

Can you find anything showing that populating 3 of the memory channels of X79, X99, or X299 ever significantly out-performs a single-channel config?

Well we really weren't saying anything about it significantly out performing other channels.... Only mention best configuration for said platforms..... (Thought it was well known this day in age that most programs dont scale with memory bandwidth all that much.)

although because you asked... there was an X79 benchmarks from legitreviews showing single to quad channel memory scaling.

Synthetics showed a difference but real world results only showed some scaling up to dual channel but mostly flat line beyond that. I'm doubting the overal results has changes all the much if x99 or x299 was tested.

http://www.legitreviews.com/ddr3-memory-performance-analysis-on-intel-x79_1779/3
 

Intel went with interleaving memory rows across available channels with Nehalem because operating the channels independently reduces average access latency and produces better overall performance. Memory is still interleaved today.

https://software.intel.com/en-us/articles/how-memory-is-accessed
"Interleaving is a technique for spreading adjacent virtual addresses within a page across multiple memory devices so hardware-level parallelism increases the available bandwidth from the devices – assuming some other access is not already using up the bandwidth. Virtual addresses within a page are mapped to adjacent physical addresses, so without interleaving, consecutive adjacent accesses would be sent to the same memory controller and swamp it."
 

Thanks for that. Rather than motherboard manuals, I had focused on looking for other information on Intel's site, such as a data sheets and a tech note I once found which explained why my 1.35v DDR3-1600 instead ran at 1333. Turns out that I had to replace with 1.5v. But it also mapped out slot occupancy.

It occurred to me that for multi-threaded performance, they could get most of the same benefit by assigning each memory controller a contiguous range and just interleaving at the page table level. This is something like what I assume GPUs probably do.


I was just talking about synthetic benchmarks, which should show benefit from any concurrency in memory-channel accesses.

As you say, most games do quite well with dual-channel. I've seen server and workstation benchmarks where quad-channel provides up to about 80% improvement over dual.
 

Thanks for replying with link, but I was saying your earlier post only made sense to me (in context) if you were talking about concurrent operation of non-interleaved channels. So, I was asking if that's what you meant and if we know whether they do that. But it's a fairly moot point.

BTW, I get what happens when memory channels are mapped to contiguous ranges. That setup is only any good for highly-threaded workloads (like on a GPU).
 


Interesting. The author states that Turbo Boost is only dual core. That's not correct. Intel has different TB freq's dependent upon the number of active die.
 
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