Upgrading And Repairing PCs 21st Edition: Processor Specifications

Status
Not open for further replies.

ojas

Distinguished
Feb 25, 2011
2,924
0
20,810
For example, if you live on a street in which the address is limited to a two-digit (base 10) number, no more than 100 distinct addresses (00–99) can exist for that street (102). Add another digit, and the number of available addresses increases to 1,000 (000–999), or 103.
Should be 10^2, 10^3, and in the next para, 2^x.
 

ojas

Distinguished
Feb 25, 2011
2,924
0
20,810
Note: Early versions of EM64T-equipped processors from Intel lacked support for the LAHF and SAHF instructions used in the AMD64 instruction set.
This was very interesting, considering both instructions were supported even by the humble 8086.
 

spookyman

Distinguished
Jun 20, 2011
670
0
19,010
I have one still from 18 years ago. Still one of the best tech books I own. Though mine was just starting to touch the Intel Pentium processor. It even covered IBM's PS/2 computers and technology. Its amazing how much more hardware intensive PC's were back then they are now.
 

ojas

Distinguished
Feb 25, 2011
2,924
0
20,810
I ended up buying the 19th edition after last year's excerpts on Tom's Hardware, the 20th wasn't available in India then.

These sections seem more or less unchanged, except for the mention of Ivy and Vishera, and i think the CPU-z screenshots are new as well.
 

AndrewJacksonZA

Distinguished
Aug 11, 2011
599
124
19,160
Apparently they were missing from the early 64bit CPUs from AMD and Intel. They appeared in March 2005 for AMD CPUs and June 2005 for Intel CPUs
https://en.wikipedia.org/wiki/X86-64#Older_implementations

Yet at the very least the 80386 supported them:
http://css.csail.mit.edu/6.858/2011/readings/i386/LAHF.htm

So it appears that it was an early-64 bit CPU issue only.
 

ta152h

Distinguished
Apr 1, 2009
1,207
2
19,285
I could only get to page three before being thoroughly disgusted by the lack of knowledge of the writer. How can he be writing books, without actually knowing the material?

The Prescott introduced 64-bit to the Intel world, not the Core 2. Kind of common knowledge. The Athlon XP had a 36-bit address bus? I don't remember ever seeing that.

Then we go to the misinformation about the 8086/8088 to 386.

In actuality, there were four modes in the 80386. Real, Virtual 86, Protected 286, and Protected 386. Yup, four. And no, Windows 3.0 was not expected to run on an 8088 or 80286, because it DID use Virtual 86, which those processors could not support. You know, the part where they let you go from one DOS task to another. That was in the hardware. And that hardware started with the 80386.

Moreover, the 80286 did NOT have the same instruction set as the 8086. Only in real mode did it. And why do you suppose it was called real mode? Maybe because the addresses were not virtualized? The 80286, as mentioned above, did have virtual addresses in what was called the 80286 Protected Mode. It not only ran Real Mode apps much faster, but when in Protected Mode was very capable of running multitasking Operating Systems, something that could not be done well on the 8086. It also increased the memory bus to 24-bits, albeit still using 64K bit segments.

OS/2 1.x was the best example of an OS using 286 Protected mode, although any software using "Extended Memory" was taking advantage of the greater addressing of the 286, albeit in an inelegant way.

I stopped reading after page three, as it's just discouraging to think people are writing books without being accurate. OK, so we have the author that got it wrong, fair enough, but what about the people who are supposed to error check it. I certainly don't know everything, and I know this stuff, and it's pretty basic. No one caught this? Are you kidding me? The 286 stuff might be a bit far away, but not knowing that x86-64 first appeared in the Prescott line is really difficult to understand, and is very basic. This is made more so because of all the rumors that the processor was made to support it, but Intel was hiding it so as to not undercut the Itanium. In time, it was proven true.

Please, don't spread misinformation. Someone will repeat this stuff, and then someone else will, and it becomes 'fact' despite being wrong. If you publish a book, make a friggin effort! I'm sure I could errors the rest of the way, but it's just too annoying for me to wade through this rubbish.

By the way, the term CPU bus is an ambiguous one. The CPU has multiple buses, and if you used that term with me, I'd wonder which one you were referring to. Find a more accurate term, like PCI-E bus if that's what you are trying to say.
 

ezorb

Distinguished
Jul 13, 2010
20
0
18,510
I feel that this is bellow the level of this website, even below the level of Maximum PC (which has a great podcast), this is the book my grandfather would buy if he wanted to try his hand at build a PC
 

ta152h

Distinguished
Apr 1, 2009
1,207
2
19,285
I could only get to page three before being thoroughly disgusted by the lack of knowledge of the writer. How can he be writing books, without actually knowing the material?

The Prescott introduced 64-bit to the Intel world, not the Core 2. Kind of common knowledge. The Athlon XP had a 36-bit address bus? I don't remember ever seeing that.

Then we go to the misinformation about the 8086/8088 to 386.

In actuality, there were four modes in the 80386. Real, Virtual 86, Protected 286, and Protected 386. Yup, four. And no, Windows 3.0 was not expected to run on an 8088 or 80286, because it DID use Virtual 86, which those processors could not support. You know, the part where they let you go from one DOS task to another. That was in the hardware. And that hardware started with the 80386.

Moreover, the 80286 did NOT have the same instruction set as the 8086. Only in real mode did it. And why do you suppose it was called real mode? Maybe because the addresses were not virtualized? The 80286, as mentioned above, did have virtual addresses in what was called the 80286 Protected Mode. It not only ran Real Mode apps much faster, but when in Protected Mode was very capable of running multitasking Operating Systems, something that could not be done well on the 8086. It also increased the memory bus to 24-bits, albeit still using 64K bit segments.

OS/2 1.x was the best example of an OS using 286 Protected mode, although any software using "Extended Memory" was taking advantage of the greater addressing of the 286, albeit in an inelegant way.

I stopped reading after page three, as it's just discouraging to think people are writing books without being accurate. OK, so we have the author that got it wrong, fair enough, but what about the people who are supposed to error check it. I certainly don't know everything, and I know this stuff, and it's pretty basic. No one caught this? Are you kidding me? The 286 stuff might be a bit far away, but not knowing that x86-64 first appeared in the Prescott line is really difficult to understand, and is very basic. This is made more so because of all the rumors that the processor was made to support it, but Intel was hiding it so as to not undercut the Itanium. In time, it was proven true.

Please, don't spread misinformation. Someone will repeat this stuff, and then someone else will, and it becomes 'fact' despite being wrong. If you publish a book, make a friggin effort! I'm sure I could errors the rest of the way, but it's just too annoying for me to wade through this rubbish.

By the way, the term CPU bus is an ambiguous one. The CPU has multiple buses, and if you used that term with me, I'd wonder which one you were referring to. Find a more accurate term, like PCI-E bus if that's what you are trying to say.
 

hardrock40

Honorable
Oct 2, 2013
14
0
10,510
Really nice article well worth the read. Was there a few errors yes but also there was a ton of info that a lot of people will be able to use.
 

tomfreak

Distinguished
May 18, 2011
1,334
0
19,280
1. Explain to me how/why a Intel went from Core 2 large 6MB L2 cache to 256kb L2 cache + L3? Since L2 is much more important than L3

2. Since L3 is pretty much a much smaller factor in cache miss, wouldnt it be much better to just take away the L3 for die size saving and add more cores on it?
 


Speed.

The L2 cache on the SB and beyond chips is incredibly fast, nearly as fast as L1 cache. It's very hard to keep the latency down with large caches so they instead moved the bulk caching to L3 and made L2 just a slightly bigger version of L1.
 
Status
Not open for further replies.