News Vendors Prep ATX12VO Motherboards Ahead of Intel 12th Gen Alder Lake Release

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You are clearly not thinking at this like an Engineer!

Quite the rich accusation coming from the guy who keeps spewing out mostly disjointed and barely coherent blobs of techno-babble. You know some of the jargon, enough about it to slap random pieces together in a semi-coherent fashion for trolling purposes and that's about it.

Any electrical engineer worth its salt would agree that 12V power distribution is more efficient than 3.3V and 5V and that the entire industry should go 12VO so intermediate 3.3V and 5V regulators can be eliminated - the cheapest and most efficient intermediate regulator is no intermediate regulator.

 

[ginthegit]

Quite the rich accusation coming from the guy who keeps spewing out mostly disjointed and barely coherent blobs of techno-babble. You know some of the jargon, enough about it to slap random pieces together in a semi-coherent fashion for trolling purposes and that's about it.

Any electrical engineer worth its salt would agree that 12V power distribution is more efficient than 3.3V and 5V and that the entire industry should go 12VO so intermediate 3.3V and 5V regulators can be eliminated - the cheapest and most efficient intermediate regulator is no intermediate regulator.

LOL, so in other words you dont understand PWM in terms of its tech, you don't even understand the dynamics of BJT's vs FETs. Lol. It was you who was spewing the incoherent nonsense and I have just got you on it.

You see, when I put the information about datasheets

https://www.farnell.com/datasheets/2258640.pdf

Now have a look at page 3 which talks about efficiency. Pfft you complete fraud. You have absolutely no knowledge of these devices.

Now have a look at the efficeincy of this Analog Devices low power version, and on page 3 it talks of Efficiency at max current draw (100% power) and look how low it goes... You complete liar novice.

29% at max load LOL, this Tech is soosoooooooooosoooooooo Efficient. You logic is novice and your research is laughable.

Now have a look at this next one where they do an intel spin

https://power.murata.com/pub/data/power/MYBSC0128CAZT.pdf

Again Page 3, and this is for a up to 75 volt version. You get a max efficiency of 92% when at half load 48 volts and half load current. Oh and look at the temprature 25degrees, at which under fukll load you will never have it that low.
Now look at page 10 and all is revealed. Like I said, the graphs in the back tell the whole story. It i giving an efficiency at 25 degrees, wow, and look at the internal components in the diagram... oh I forgot you aren't familiar with them.... Lol Now look at the graph under it, this is what I was telling you, look at these ripple spikes on the output. This is because to get their efficiency, they had to cut corners and avoid the regulator stage, I WOULD NOT TRUST THIS CHIP IN A COMPUTER.
Not only is this chip boasting high efficiency at half load and 25 degrees only, unlike the first Data sheet, this one does not give you averages but a fixed value at a fixed best case load... It is false advertising. And this is why Analog Devices has more customers, because Unlike intel, they are more honest.
These Chips are Diminishing returns on power.... and that my numpty friend is how I get information, pray tell how you get yours?

Oh and i just read up on the DC converters in power stations, lol, to get anywhere near the efficiency they want they have the whole system immersed in oil or encapsulated in Helium.... Nice mate nice...

https://www.xppower.com/products/dc-dc-converters?q=c26c4989-7873-409d-b24a-c26ebdf23baa

Nice also look at the above, a surface mount chip (motherboard based) has a max power rating of 15 watts... Looks like I guessed right... So not only will they have to run them at 7.5watts, they also have to keep them cool and they have to have several of them side by side... LOL

Now please, give up while you are behind! Or at least give some actual evidence to back up your quality knowledge on the subject... not just ProIntel wishful thinking.

 

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LOL, so in other words you dont understand PWM in terms of its tech, you don't even understand the dynamics of BJT's vs FETs. Lol. It was you who was spewing the incoherent nonsense and I have just got you on it.

You see, when I put the information about datasheets

https://www.farnell.com/datasheets/2258640.pdf
https://power.murata.com/pub/data/power/MYBSC0128CAZT.pdf

Only a lunatic would use fully-isolated DC-DC converters for low voltage loads sharing a ground plane and a handful of non-isolated single-ended control signals. Also, the first one is only designed for mW-scale loads and efficiency doesn't matter much at such a small scale.

Computer components that need a couple of low-voltage rails from 12V would use something like this:
https://www.maxlinear.com/ds/xr77103-a0r5.pdf
Three channels with integrated synchronous rectifiers, only needs the external inductors, capacitors and feedback components to achieve 80-90% efficiency bringing 12V directly down to 1.2V or providing 3.3V and 5V for SATA ports either on-motherboard or in-connector.

While 3.3V or 5V to 1.2V may be 3-4% more efficient, you need to keep in mind that 3.3V and 5V in modern PSUs comes from 12V getting bucked down to 3.3V and 5V first, so the overall efficiency of 12V -> 5V or 3.3V -> 1.2V is still worse than direct 12V -> 1.2V.

 

[ginthegit]

Only a lunatic would use fully-isolated DC-DC converters for low voltage loads sharing a ground plane and a handful of non-isolated single-ended control signals. Also, the first one is only designed for mW-scale loads and efficiency doesn't matter much at such a small scale.

Computer components that need a couple of low-voltage rails from 12V would use something like this:
https://www.maxlinear.com/ds/xr77103-a0r5.pdf
Three channels with integrated synchronous rectifiers, only needs the external inductors, capacitors and feedback components to achieve 80-90% efficiency bringing 12V directly down to 1.2V or providing 3.3V and 5V for SATA ports either on-motherboard or in-connector.

While 3.3V or 5V to 1.2V may be 3-4% more efficient, you need to keep in mind that 3.3V and 5V in modern PSUs comes from 12V getting bucked down to 3.3V and 5V first, so the overall efficiency of 12V -> 5V or 3.3V -> 1.2V is still worse than direct 12V -> 1.2V.

Wonderful wonderful, Not only did you find one with actauly worse data than what i found, this only further Proves my point. Again all the claims you make are from the Ideal data set back at page 10/19. And my point is proved on the efficiency graphs with the misleading data.

Now lets focus on the data that deals with the core of the chip, and we an see that just at optimal tempratures and at 0.5 Amps only (being as on page 3 they are saying that typical load current is 0.5A (which is not for them to decide; and just happens to be the best data, and I doubt they are going to hit exactly on 0.5A. If anything it will be less for a low power chip. The roll off tells the story of typical Heavy Max power losses which are worse typically when Xciruit is over the value of Xout and the roll off is terrible. There are no such problems with Inductor based power supplies. The problems with DC couplings that are not properly terminated with identical impedances is indeed what we are seeing here.
So in essence you have proved my point, so thanks for that. So if the Intel CPU core does draw exactly 0.5 Amps and created no heat, then the claims for this chip state 87% at best (which is bettered by the older tech) and 84% best case for the lower voltage with worse termination voltage under loads of 0.4 Amps... So what we are saying is that the systems (all of them must be drawing at least 0.4 amps just to be effcient (which is exactly my point), and I'd love to see how they intend to do that concidering CPUs pull Current on Demand, and do so fairly erratically considering that the Operating system and the BIOS choose the correct draw based on demand by internal processes and user control. This tech now looks more pathetic than ever. Basically at low load and high load, these chips are crap. And we are not even getting into temprature.
This has allowed me to draw conclusions on why this is a failed tech, and really its only uses are constant current drawing devices, not ones that are dynamic like PC's. Phones are Ok with this as their power demand can be mitigated by the fact that the lower clocking and screen use keeps the draw of power fairly constant, and they can also have switchable DC to DC systems that can deal with a few different uses (like when screen is off and on).

Again these efficiencies are Lab levels and at a stated temprature of 25 degrees C and if your standard PC is working with temps between 30 and 40 C, then I guess the Analogu Devices system is bang on with low efficiency, and this is just a gimmick.

And it doesnt matter even if it is common groundplaning, the whole point was I was showing was systems at both ends of the power scale.

So again, the efficiency of the 3.3v is the best case and 5v is lower and even worse are the efficiencies for the core of the CPU which are around 85% at best case scenario. The output is indeed more stable with only 0.1 volts fluctuation on the average on the clock switch for both up and down, but even that is not ideal.

So rather than a proper regulator they have themal shutdown and over current protection, which i gather is done through thermal throttling.
You have done nothing to further your case, it has only made mine stronger. These efficiencies are no way near what you were blowing out except for the 3.3v.

 

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You have done nothing to further your case, it has only made mine stronger. These efficiencies are no way near what you were blowing out except for the 3.3v.

And where does your 3.3V come from? From a 12V to 3.3V DC-DC converter, so you have to add that 5-40% conversion loss to all of your 3.3V figures.

 

[ginthegit]

And where does your 3.3V come from? From a 12V to 3.3V DC-DC converter, so you have to add that 5-40% conversion loss to all of your 3.3V figures.

What? This comes straight from the Lab case Graphs. The ones that are on page 10 I believe. They state for themselves the transient loss graphically and the 3.3v is the higest perventage efficiency according to their claims. Not mine.

I am sorry if your own datasheet proves my point and not yours, but I am sorry, reading through the datasheet only confirms the poor science behind the idea. I am just trying to figure out how they are trying to mitigate the low load losses, I can only imagine there has to be a wasteful potential divider somewhere. I guess it is the one by the Inductor that can take up to 4A... But being as that reduces efficencys at that draw (75%) then I guess your efficiency argument collapses to the ground.

In fact I cannot find anywhere how they mitigate the low load losses, so maybe you can enlighten me! Max power theory 101 says that balancing loads is important, which is why digital based equipment terminate against each other.

I understand the modulation Idea, but the ways in which to balance it to terminate a dynamic load of which a perfect amount at low power is 10% or near, this device has catastrophic failures. Or do they modify the frequency of operation to offset the losses, and use the old frequency trick to dynamically change impedance.

 

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What? This comes straight from the Lab case Graphs. The ones that are on page 10 I believe. They state for themselves the transient loss graphically and the 3.3v is the higest perventage efficiency according to their claims. Not mine.

Again, that 3.3V does not magically appear out of thin air with 100% efficiency. In modern ATX PSUs, it would come from a 12V to 3.3V DC-DC converter, so before your hyper-efficient 3.3V to 1.2V converter can even start doing its thing, it already has a 5-40% efficiency handicap from the 12V to 3.3V conversion.

With a straight 12VO system, you eliminate the 12V to 3.3V conversion by going straight from 12V to the 1.xV that most modern stuff needs, which makes everything 3-5% more efficient.

 

[ginthegit]

Again, that 3.3V does not magically appear out of thin air with 100% efficiency. In modern ATX PSUs, it would come from a 12V to 3.3V DC-DC converter, so before your hyper-efficient 3.3V to 1.2V converter can even start doing its thing, it already has a 5-40% efficiency handicap from the 12V to 3.3V conversion.

With a straight 12VO system, you eliminate the 12V to 3.3V conversion by going straight from 12V to the 1.xV that most modern stuff needs, which makes everything 3-5% more efficient.

Pfft, And you do realise that the 5 - 40% depends on the full load of the power supply. So having a 1000 w and above means the load is very low, so close to the 5% margin, and I am sorry, but your DC to DC has an even more pathetic job than this is the load is too low or too high.

It is simply better to keep things as they are rather than add complexity that increases cost and makes efficiency difficult to stabalise. Simply said, your own Datasheet proves this tech is more poor than good with efficiency, and you still havent answered my question... How do they expect to balance impedences when the load is too low and too high?

 

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It is simply better to keep things as they are rather than add complexity that increases cost and makes efficiency difficult to stabalise.

Eliminating intermediate DC-DC converters ELIMINATES the cost and losses of those intermediate DC-DC converters while also making the whole system cheaper. The most efficient energy conversions are the ones you can get rid of.

https://pasteboard.co/K3a32Of.png

 

[ginthegit]

Eliminating intermediate DC-DC converters ELIMINATES the cost and losses of those intermediate DC-DC converters while also making the whole system cheaper. The most efficient energy conversions are the ones you can get rid of.

https://pasteboard.co/K3a32Of.png

Why do you keep sending me these Diagrams proving what i said above. I gleaned these results from the Graphs of you data sheet. The fact that it admits efficiency of as low as 34% is absurd, this is exactly my point.

Your diagram tries to prove that 1.2 volts DC to DC converter can go from 95% all the way down to 34% which is a lie. The maximum efficiency of your graphs said it was 87% max at at half load and 25 degrees. Both absurd to claim considering this considering (unlike Apple and Consoles standarised hardware, has varying loads (unless its OEM where it can be controlled to a greater degree as they are not usually upgraded except memory). Which is what I said since the beginning.

The fact is you will never get the 87% unless you are within the first 5-10 mins of operation, and once the system heats up to normal motherboard tempratures (up to 45 degress) you are now near twice the designed thermals and down to about low 70's. Start to use these on heavy systems and this will go below 50%. I know my electronics mate, and all you are doing is showing that what I gleaned before about your Datasheet was entirely correct.

What is worse, is when you place the DC to DC converters on the Motherboard, you effectively make it impossible to make power readings (whithout a specifically designed sub circuit on the motherboard to measure input power vs output power). This is all a fake tech show, and the fact that they are tricking the Low power regulations in covernment with Fake stats shows how far things have dipped in terms of standards.

The fact that the End to end efficiencies can go so low is eye bleeding, and you really need to ask yourself the question, when does the power efficiency go below 70% and for what reason? You will find it is for the reasons I explained above.

FACT; these DC to DC converters are nonsense for efficiency, they are more wasteful that their AC 3.3v brothers. And it does not matter that they ise a DC to DC converter to get it from 3.3v to 1.2v, because the step down is 50% and easy to control for ripple and easy to keep impedence matched.

Conclusions:

1. Taking away the 3.3v and 5v lines will = massive efficiency losses.
2. You will not be able to prove the power loss is due to the DC to DC 12vo system when integrated on the motherboard. (typical Intel bad science behaviour).
3. The whole patent of Intels 1995 failed attempt to have it standardised was because at the time these problems were flagged up, but now that Intel has a dominant market and slush funds, it can pay partners to adopt bad tech for backhanders.
4. Intel nutters who just worship Intel will buy it because Cognitive dissonance is a real thing and you have it in spade loads.
5. Intel is desparate and now, IBM is giving them a boost with the 3nm lithography, because the Intel monkeys (desipite massive R&D) couldnt stop AMD from catching up, competitive Fab plants over taking them. And 3D FinFETs not giving them the control and stability they want under high power and hence they are stuck in the 14nm except from lower power envelope chips.

By all means, keep sending more information proving my argument, it is enjoyable for me to explain tech to you in detail, and then you send proof of my diagnostics relating to power loss and Intels poor science.

https://www.networkworld.com/article/2239461/intel-and-antitrust--a-brief-history.html

Dec 16 2009 tells me all I need to know about Intel and its tech!

 

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FACT; these DC to DC converters are nonsense for efficiency, they are more wasteful that their AC 3.3v brothers.

Try powering modern CPUs and GPUs that can require 250+A peak current from a 3.3V rail, you will need cables able to bear close to 100A between the PSU and CPU/GPU with PSUs having to be built to handle 200-500A at 3.3V. Good luck fitting that amount of copper in reasonable size transformers for AC-DC conversion and packing all of the synchronous rectifiers needed to minimize losses close enough to the transformers to make it efficient. Maintaining 5% tolerance on 3.3V vs 12V is also ~4X harder since you simultaneously have that much less headroom and that much more current to deal with.

 

[ginthegit]

Try powering modern CPUs and GPUs that can require 250+A peak current from a 3.3V rail, you will need cables able to bear close to 100A between the PSU and CPU/GPU with PSUs having to be built to handle 200-500A at 3.3V. Good luck fitting that amount of copper in reasonable size transformers for AC-DC conversion and packing all of the synchronous rectifiers needed to minimize losses close enough to the transformers to make it efficient. Maintaining 5% tolerance on 3.3V vs 12V is also ~4X harder since you simultaneously have that much less headroom and that much more current to deal with.

What has this got to do with anything. The best part about split voltage powersupplies with 3 different rails, is that I can paick and choose which of the voltages I can use for various aspects of operation. 3.3v and indeed 1.2 volts are primarily used for Signaling and decision based logic based on the Sequential logic systems that make up the CPU and all the control chips on every chip. 5 volts is generally used for small scale power and mechanical elements, and12 volts is needed for juice in its purest form running the Power amplifiers Opamps et al. All the voltages have their place and it is best staying as they are.

Having a PSU system that handles Most of the power is a sensible methodology. It is easier to control, does not interfere with the Motherboard (except for the wiring) and is largely efficient over the whole range of required power that a system will require. the 12VO systems are however not. They depend on Load temprature and other dynamic systems to make sure that the Impedance keeps to maximum power transfer conditions.

This whole technology does not yield the promised results under normal operation, and only reaches the 93% with certain power rails, and not all of them, only under lab consitions. The Liars at intel have tricked the Government into buying into its ultra efficiency, which is largely BS.

At the end of the day, Digital based systems are wasteful, as they are using power all the time to make decisions one way or another and is inherent in these synchronous systems. If you really want to save money and power, Hardware is about as good as it can be. What they should be focusing on is Software or automating Master and slave cpu based systems (like the old Cell).

But no, the whole ecosystem is all about standardisations, and forcing each other into them, and not for the best. Thank God Rambus, failed, thank god that Intel stole sections of the A64 architecture during AMDs brief reign in 2003. Intel fights hard and dirty.

 

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They depend on Load temprature and other dynamic systems to make sure that the Impedance keeps to maximum power transfer conditions.

Maximum power transfer based on impedance is a controlled impedance signal transmission line thing, not a power distribution thing where 50% of the power gets pissed away at the source by matching impedance with the transmission line for signal integrity reasons.

For efficient power distribution, you want the power distribution network to have the lowest impedance possible within practical limits so as close to 100% of the power produced gets consumed by the loads, not the network.

 

[ginthegit]

Maximum power transfer based on impedance is a controlled impedance signal transmission line thing, not a power distribution thing where 50% of the power gets pissed away at the source by matching impedance with the transmission line for signal integrity reasons.

For efficient power distribution, you want the power distribution network to have the lowest impedance possible within practical limits so as close to 100% of the power produced gets consumed by the loads, not the network.

Which is why it is set to 50 ohms. But they aim to design around 75 ohms.

But you cannot avoid the max power theory, not for any system. The signal boucing wreaks havok within the system as the Magnetic field holds the unterminated signal and it will reflect back through the line. It does not need to be just related to the power , it is a simple fact. Devices like headphones etc must be properly terminated or you end up with problems. Who bloody well taught you your electronics?

Is this what they teach in American colleges? Have you actually done studies on signal bouncing, because this was a second year learning assignment. Proper termination is needed with every bit of power, not only for max power output, but for signalling too.

Most transformers are designed to have a set impedance, it is designed into the system. Simple as that. As soon as you pass a current at a frequency through the coils, you get an impedance, and without matching it or dealing with the reactive energy due to phase change, you end up with more uncontrolled power and loss. But as with all digital systems of control and signaling, power is never considered an issue because the control and signaling is more important. But even TTL and CMOS are terminated properly.

Seriously where are you getting your information from?

 

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Devices like headphones etc must be properly terminated or you end up with problems.

Transmission line effects are insignificant when your cables are under 1/100th the shortest wavelength going through them and impedance matching is only needed to avoid those effects. You aren't going to have any impedance-related issues with headphones unless your audio cables are over 10km long.

The only thing you need to know the headphones' impedance for is to determine what the maximum driver voltage needs to be to stay within their rated power.

 

[ginthegit]

Transmission line effects are insignificant when your cables are under 1/100th the shortest wavelength going through them and impedance matching is only needed to avoid those effects. You aren't going to have any impedance-related issues with headphones unless your audio cables are over 10km long.

The only thing you need to know the headphones' impedance for is to determine what the maximum driver voltage needs to be to stay within their rated power.

really, so when we pulsed a signal with 30 ohms termination on normal BNC cable back in the 90's I just imagined the signal bouncing. Because a metre of BNC cable is not 10KM long.. Seriously, where are you getting your knowledge From.

Not only do earphones brag about their 60 to 75 Impedance values as a selling factor for good sound output and proper termination, I believe that you are making utter trash up . Seriously, you are just reading trash from websites, you are not a trained engineer. All I hear from you is specific case knowledge you read through in some article, then you blanket your knowledge over the whole thing.

Note also that BNC cabling was for the old network connectors for PC's as I was old enough to own one before the Cat5 became a standard. We enjoyed daisy chaining BNC's, but you always had to remeber, terminate the ends or you end up with problems.

But of course, those problems were our imagination because they were not 10km long. Sheeesh, will you just stop.

The only thing you need to know the headphones' impedance for is to determine what the maximum driver voltage needs to be to stay within their rated power.

Good lord, here you go again contradicting yourself. Rated power is related to max power theory. Driver voltage and associated currents have to be properly phased to make sure that the reactive energy is at a minimum (or a maximum if the load is capacitive or inductive, which in the case of speakers they are). Driver voltage lol, I wonder why that has to be a set level... Duh!

 

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really, so when we pulsed a signal with 30 ohms termination on normal BNC cable back in the 90's I just imagined the signal bouncing. Because a metre of BNC cable is not 10KM long.. Seriously, where are you getting your knowledge From.

Looks like the concept of wavelength flew 10 miles over your head. You don't need termination when wavelengths are so long relative to cable length (ex.: audio where most cables are under 10m long) that the entire transmission line can be considered at uniform potential, there is no potential difference for the signal to reflect to in any meaningful capacity.

 

[ginthegit]

Looks like the concept of wavelength flew 10 miles over your head. You don't need termination when wavelengths are so long relative to cable length (ex.: audio where most cables are under 10m long) that the entire transmission line can be considered at uniform potential, there is no potential difference for the signal to reflect to in any meaningful capacity.

It has nothing to do with potential. I don;t know what science you learned, but it is not proper electronics. We learned signal bouncing from small lines. If you never explored it then bully for you. It still happens whether you know of it or not.

So BNC lines had terminators for no reason I guess... I guess Science bends its rules for you....

 

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It has nothing to do with potential.

There can be no current, no power and no reflections without a potential difference.

 

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For if at Short circuit potential is 0 and current is infinate, then no power or energy can flow, but yet it does and it does it at maximum amount too. Try explaining that one.... That is why I am a good Engineer!

The ideal (0V) short itself can pass all the energy you want without dissipating any power. All of the power gets dissipated by the source's internal resistance and wiring connecting it to the short.

If you really were an engineer, you appear to be seriously out of practice.

 

[ginthegit]

The ideal (0V) short itself can pass all the energy you want without dissipating any power. All of the power gets dissipated by the source's internal resistance and wiring connecting it to the short.

If you really were an engineer, you appear to be seriously out of practice.

So when we are looking at what gets damaged between an aircraft battery and the Wire that it is connected to, why is it the wire that gets damaged, Because the Battery on aricraft systems is designed to take the thermals, and the Wire isn't. So again the Answer is flawed. Note also to have the Power pure nonreactive and actually dissipate, you need to have the battery internal resistance and another resistance to terminate it, namely the wire. The damage to the battery is purly thermal based on Electron migration, where as the wire that creates the short becomes were the power loss occurs, because the electromagnetic field cannot be induced sychronised to the current flowing (Tesla theory) not you nonsensical Electron migration theory that you so worship. Want me to explain how Tesla propegated energy in short circuit without damaging the source. Geeeeeez.

OK! lets be frank here, the battery only has an internal resistance for standardizing voltage on a cell. Now explain how this works with a pure torroid with a transformer where there is no resistance (or so little of) in the wire. Pffft, Have you ever thought of how solinoids when matched with a load solenoid can transfer (with losses) to a secondary without shorting.

Now look at a few threads reflcting on the science behind the 0 resistance (ideal laws) and how they always explain it away with the XL nonssense. This is not the reason because as we know with Power and phase, there is a reason why we use capacitive banks to adjust the phase to get a power factor arounf 95-97%. Because the reactive energy in todays physics is entirely useless and considered waste energy (unless you run a reactive load like motors or inductive based rotary systems.

Please By all means explain the reason for it, because even the best minds cant agree on it! Might it be becasue power prefers to travel in magnetic form? and the fact that Power factor correction tries to focus on a 0.95 PF explains where 5% of the enegy waste is going in the system. Tesla used RESONATORS to get around this problem as they offset thermal drift and kept the frequency constant so long as you could keep the capacitive bank cool.

So when you have a single solenoid you have heat, you place another one next to it and no heat. Magic!

And yes this is relevant to the 12VO argument as i am again defensing the use of solenoid based Step-down approach...

Did you never ever ask your teacher to explain this effect? or did you just read the vague textbooks.
So without the use of back EMF and Impedance that are mutualy exclusive!

Back emf would produce a reactive votlate in the opposite direction causing the phase to slip from 270 to 90 degrees. No the only place the Back Emf appears is the scondary coil. Because when the Primary coil has no matched Mutual impedance, the whole back EMF is nonexistant... how is that?