We're reaching the molecular limits of silicon with these sizes, that's the major hurdle they're researching to overcome. When getting smaller, the leakage problems go up since things are crammed closer together and it's a shorter distance for the electron to travel when leaking. But that's also why speeds go up, the travel distances are shorter. It's a tough thing to balance.
Here's a grossly oversimplfied explanation of the "nm" term in the technology, based on a course I had on VLSI chip design in engineering school: (back in the late 80's, but the concepts are still good)
Chips are designed in a square grid formation, so if you sit down to design a chip, you'd start with a piece of graph paper. The size of each square on the graph paper is the basic unit measured in nanameters. So if you're talking 90nm technology, the basic unit of measure is 90nm, and the geometry is based on 1 unit=90nm. Obviously, the smaller the unit the more things you can cram into a given area. An incredible amount of R&D goes into deciding how to construct a transister using that basic unit size. The companies that manufacture the silicon foundry equipment does all that R&D, that's why it costs billions to make a new fab or to change your geometry from say 90nm to 65nm. It's all brand new equipment to make a size change, you can't "upgrade" the foundry equipment to a smaller size.
The first 2-3 months of the course dealt with how they determine this based on material science of silicon, microelectrical properties, etc. Frankly I was lost after two classes. 8O But after all the theory was worked out, you were then free to design using the set of rules devised for that size without having to to all the ugly math and analysis. It's kind of using Lego blocks at that point, you don't worry about how to make a Lego brick, you just know how it fits with the other bricks. The www.tweak3d.net article shows how the layers and shaped of a transistor are made, but the geometry in nm is what determines the units used for the features of every part of the chip.
Chips today aren't designed at that low level anymore, the designers have libraries of functional blocks in the CAD programs they use. That intellectual property of those functional blocks are what gives Intel or AMD their advantages, and it took decades to build up that knowledge, just like a software company's intellectual property value is their library of code routines. AMD is a generation behind Intel on their geometry size, since Intel has a far bigger R&D budget and they started earlier. But AMD makes up for that disadvantage by designing more efficient processor structures and architecture. Intel bet the farm on NetBurst architecture, and they've now learned it has limitations, and Intel isn't very nimble at making major changes in thought. like AMD is. Sometimes smaller is better for a company.
The other problem with getting smaller and smaller is referred to the "Lithography". The features are made on the chip optically using masks that cast shadows. Well, at these sizes we're at, the actual wavelength of light is too big to make accurate shadows, so they've gone to X-rays and Ultraviolet lasers to make the "light". Producing features ever smaller is becoming more difficult to make smaller wavelengths to produce smaller shadows.
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