What exactly is a memory bank?

[Loading000]

I am wondering what is a memory bank and what exactly it does? Does it effect ram in any way?

 

[LilDog1291]

Can you provide an example of what you mean? A link or a source that you're seeing?

 

[nzalog]

Pretty sure it just a way to group memory.

You could say dimm 1 and 3 are bank 1 and dimm 2 and 4 are bank 2.

I don't think it's a highly technical term and can be used in different ways and even paired or not paired at all.

 

[Eximo]

Memory bank is a pretty generic term, it could be referring to the RAM itself.

 

[Flyfisherman]

Hi,

I think this will explain what a memory bank is: Techopedia: Memory Bank

Yes, it will in some circumstances use a bit of Your RAM, depending of what You're talking about here.
Best regards from Sweden

 

[Eximo]

Pretty sure it just a way to group memory.

You could say dimm 1 and 3 are bank 1 and dimm 2 and 4 are bank 2.

I don't think it's a highly technical term and can be used in different ways and even paired or not paired at all.

Normally these are referred to as channels. I think the bank would apply to all of the slots taken as a whole. But we are getting down into semantics and not any real definition.

 

[nzalog]

Pretty sure it just a way to group memory.

You could say dimm 1 and 3 are bank 1 and dimm 2 and 4 are bank 2.

I don't think it's a highly technical term and can be used in different ways and even paired or not paired at all.

Normally these are referred to as channels. I think the bank would apply to all of the slots taken as a whole. But we are getting down into semantics and not any real definition.

Being that "memory bank" is not really a highly technical term, an entire memory channel or entire dimm, or all the memory could all be considered a memory bank since even a dimm is made up a collection of memory chips.

It makes more sense for massive servers that have 8 or so add on cards that have 10 dimms each on them. You'd call the first add on card bank 1 or something like that. It's just doesn't mean anything specific.

I think the best way to sum it up is a grouping of memory.

 

[Eximo]

Not an expansive wikipedia article with only a single reference, so I really wouldn't call it definitive. I'm too lazy to look up the source material.

But similar terms are used in other fields. Capacitor bank. A single capacitor made up of many capacitors in parallel.

Battery bank, typically a battery used to charge other batteries. Though it also refers to a grouping of batteries (which themselves could be called cell banks if you wanted to get fancy)

I think we used to have a 286 or 386 that took an add-in card full of 30-pin SIMMs. Probably just called it a memory expansion card though. Also had motherboards that took extended memory modules before onboard level 2 cache was a thing.

 

[bloodroses]

It's a place to store your RAM so you gain interest off of it.

But seriously, it can refer to multiple things. When I was taking programming classes, it was a term used for the 'reserved' section of memory that we were either allowed or not allowed to write to. Same with clusters of memory based on the same highest bit value.
On motherboards, I've heard the term used to reference the group slots used for dual and quad channel memory.
With the old Sound Blaster audio cards, it was the RAM used to store MIDI samples.
There are many other examples.

 

[Pinhedd]

I am wondering what is a memory bank and what exactly it does? Does it effect ram in any way?

A memory bank is a functionally independent memory device that is constructed in parallel with other banks in order to increase the throughput of the memory architecture.

Many types of RAM and even some non-volatile storage use multiple memory banks. For the purposes of keeping things brief and not overly technical I'll detail how memory banks work in DDR3 and DDR4 SDRAM.

All DDR3 chips contain eight fully independent memory banks tied to a shared IO interface. A 4 gigabit DDR3 die (the largest capacity produced) is actually constructed from eight 512 megabit memory banks. During operation, each rank has one row open from all of the rows in its own memory; a memory bank cannot open a row in another bank's memory. When a command is sent to the selected rank, the Bank Address is used to determine which memory bank the command is to be sent to. The chip's internal decoding circuitry takes care of the rest. Since the IO bus is shared, care must be taken to avoid sending commands to banks such that the results may overlap.

Consider the following:

A CPU contains a single dual-channel DDR3 SDRAM controller.

Each memory channel is populated by two DIMMs.

Each DIMM contains two ranks.

Each rank is constructed from 4 gigabit DDR3 SDRAM chips.

Now, lets do some math.

<2 DIMMs per channel> * <2 ranks per DIMM> = 4 ranks per channel

<4 ranks per channel> * <8 banks per rank> = 32 banks per channel. Since each bank has its own open row, more banks is better!

<8 kilobits per row> * <65,536 rows per bank> = 512 megabits per bank

<512 megabits per bank> * <8 banks per die> = 4 gigabits per die

<64 IO bits per rank> / <8 IO bits per die (in this example)> = 8 chips per rank

<8 chips per rank> * <1 die per chip> * <4 gigabits per die> = 32 gigabits per rank

<32 gigabits per rank> / <8 bits per byte> = 4 gigabytes per rank

<4 gigabytes per rank> * <2 ranks per DIMM> = 8 gigabytes per DIMM

<8 gigabytes per DIMM> * <2 DIMMs per channel> = 16 gigabytes per channel

<16 gigabytes per channel> * <2 channels> = 32 gigabytes installed

Since each bank has one row out of 65,536 open, the memory controller must know the precise state of each bank under its command. The greater the number of banks installed, the greater the likelihood that the memory controller will be able to reorder and schedule a command without having to open a new row on a bank, which is a time consuming task.

DDR4 works slightly differently. Whereas DDR3 has eight fully independent banks, DDR4 has four fully independent bank groups, with each bank group having four semi-independent banks within it. The principle and mathematics behind it are the same but DDR4 has additional timing constraints not present in DDR3.