What's with the M2 socket?

[Vile]

I just heard about the M2 today and I'm like 8O
People saying the 939 is doomed and so on.
What's so great about this new socket? Say, compared to the 939

 

[ChipDeath]

Nothing really. It still has 939 pins, they're just in a slightly different configuration. The industry is moving towards DDR2 instead of DDR, so AMD had to make the switch sometime.

Because their memory controller resides on the CPU they needed a new core, which would be incompatible with the current socket 939 boards (due to their DDR support/slots), so it actually does make everyone's life easier to change the socket - If the CPU physically fits, then it is the right one for that board, kinda thing...

Note that Intel didn't have the same reasons at all for going from socket 478 to 775 - they only needed more pins so that they weren't having to force the stupid power requirements of prescott et al through only the 478 pins, and also to make the CPU more robust by sticking the pins on the mobo instead of the chip.

 

[slvr_phoenix]

**shrug** AMD is making a new set of sockets. Is there really anything else to say about it? Like always, with any socket change, the old hardware is screwed and you have to get the new stuff. There's not much else to it.

I mean, sure, we could go into technical details of why the sockets are being changed, but even that's pretty much always the same thing. More communications require more paths. More paths require more pins. That or it's about voltage. **shrug**

Such is life.

 

[paulbag]

The M2 socket actually has 940 pins, but its not compatiable with the old FX51/53 and Otpy chips.

Here's a bit more info on it: http://www.tgdaily.com/2006/01/13/amd_m2_platform_launch/

 

[apesoccer]

Hey Chip, i'm not absolutely sure of this, but isn't the memory controller already designed to work with ddr2 as well? I thought i read that somewhere...

 

[Vile]

I see, thanks for the link.

When is this new socket coming out? (In the article it said something like Q2, but I've no idea what that means =/ English is not my primary language )

So it seems there won't be much of a dif between the M2 and the current AMD64 processors, altho it says they'll now run with 512kb L2 cache only, how come some 939 64's support 1mb L2?

 

[Admiral_Cecil]

Hello,

Lets not forget Socket M2 is 940 pins. However, the current 940 pins will not be compatible due to pin configuration among other things.

 

[FlyGuy]

When is this new socket coming out? (In the article it said something like Q2, but I've no idea what that means =/ English is not my primary language )

Q2 means the second quarter of the year. The year is split up into four quarters, Jan-Mar being the first quarter, Apr-June the second and so on. The latest I have read was around May.

 

[ChipDeath]

Whoops, my bad there...

Knew it was the same number as an existing socket, but a different config...

Hey Chip, i'm not absolutely sure of this, but isn't the memory controller already designed to work with ddr2 as well? I thought i read that somewhere...

AFAIK it's different. I could well be wrong... but if I am, what would be the point of the new socket?

 

[paulbag]

Nah I read its different, thats why they need the extra pin. Its to allow DDR2 to run.

 

[Vile]

Thanks for the help FlyGuy.

So 1 more thing, why do M2 Athlon 64's only use 512kb L2 and current 939 use 1m L2?

 

[borandi]

So 1 more thing, why do M2 Athlon 64's only use 512kb L2 and current 939 use 1m L2?

I'm under the impression that the L2 is dependant on the processor. My X2 4400+ has 1mb L2, but the X2 4200+ only has 512kb.

So it would depend on the processors designed to use it.

 

[Vile]

All Socket M2 processors will be based on a common DDR2 memory controller that is validated for 333 MHz operation (DDR2-667), with only the cache size and clock speed differentiating the individual processors. There will be 2 x 1 MB or 2 x 512 KB L2 cache for the dual cores, 512 KB L2 cache for the single core Athlon 64 models and 256 KB for the Sempron series.

Not according to that =/

http://www.tgdaily.com/2006/01/13/amd_m2_platform_launch/

 

[slvr_phoenix]

So 1 more thing, why do M2 Athlon 64's only use 512kb L2 and current 939 use 1m L2?

If true, it's probably because the extra 512KB wasn't actually accomplishing much. Well, I know that it wasn't really accomplishing all that much, but more that AMD actually admits that it doesn't. :lol:

I mean why screw up x percentage of chips from cache failures for a cache that doesn't need to be so large in the first place? Just shrink the cache back down, still have nearly identical performance, and improve yields.

 

[borandi]

All Socket M2 processors will be based on a common DDR2 memory controller that is validated for 333 MHz operation (DDR2-667), with only the cache size and clock speed differentiating the individual processors. There will be 2 x 1 MB or 2 x 512 KB L2 cache for the dual cores, 512 KB L2 cache for the single core Athlon 64 models and 256 KB for the Sempron series.

Not according to that =/

http://www.tgdaily.com/2006/01/13/amd_m2_platform_launch/

Ah well I said it was dependant on the processor at least But yes, the A64 single cores will be 512 L2 in that case - but some of the dual cores will be 1mb.

 

[Vile]

I see, thanks Phoenix and everyone

 

[slvr_phoenix]

Not a problem. That's what we're here for.

I think.