There are two other limiters aside from PPT: there's EDC and TDC too. And, of course, core temperature.
It's probably peaking the EDC (Electrical Design Current) limit instead; EDC is the peak current a processor is allowed to draw during a transitory processing "spike" (intended to be a protection for weak VRM's). EDC will peak out before either of PPT or TDC during certain AVX instruction functions, which is exactly what Cinebench does.
These three parameters are what you play with when tweaking PBO settings. I'm not sure you can do that with an x3d processor but even if you did increase the EDC settings you might find it actually losing performance. I think that's because core temp starts to limit performance if you let core currents run too high during sustained periods of transitory AVX spikes. Sometimes, actually reducing EDC from the stock settings allows the processor to stretch it's legs a bit better.