I like having friendly conversations too. Its a lot better than being told by wusy that he is going to rape me.
"He'll be raped by me before that happen, I assue you."
In any case, I'm probably going to get yelled at:
1st because this is such a long post and
2nd because a lot of this is congecture.
All I can say is that all may conjecture is based on true information, and I just felt like speaking my mind. Besides josh_1413 asked for my thoughts, well here they are:
Anyways, I don't still don't think that bandwidth issues are that significant for Intel. It was for the Pentium 4 but the Pentium M seems to need less bandwidth. While the Pentium 4 showed a jump in performance moving from 533MHz FSB to 800MHz, Dothan doesn't seem to benefit significantly from the move from 400MHz to 533MHz. In fact, Dothan doesn't appear to use all of the 533MHz FSB. This would mean that Intels next generation dual core processors are given more than enough bandwidth by a 1066FSB. This FSB would be supplied by 800MHz dual channel memory, which likewise offers more than enough bandwidth. Dual core Woodcrest chips are also going to have even more headroom if needed with a 1333MHz FSB.
The only complication is Cloverton, the 4 core version of Woodcrest. For whatever reason Intel decided to limit it to a 1066MHz FSB. Now if this was 4 completely separate cores it would be severly bandwidth limited. However, it isn't. Cloverton has a 16MB shared L2 cache. This means that not all four cores need to request data. Often, the data a core needs is already available in the L2 cache since it was added there by another core. This will help reduce the need to access the FSB. As well, a lot of overhead is reduced by advanced prefetching techniques. Both Prescott and Dothan already had excellent ones for data prefetching as well as loop detectors to avoid pipeline misses and extra requests for data. This likewise frees up FSB bandwidth. Overall while Cloverton will be limited by bandwidth it isn't as severe as it appears.
Besides, Cloverton appears to be a short lived product. Intel is beginning to be very aggressive with its pace of technology transition. Yonah is coming out in January on a 65nm process and is to be replaced in 6 months by Merom and the rest of the next generation. 6 months after that, the entire Merom family will be replaced by a 45nm generation. Intel's 45nm process looks very promising as it solves leakage problems and will be available for early 2007. Woodcrest itself will be replaced by Harperstown and Cloverton (4-core Woodcrest) will likewise be replaced. Cloverton's replacement will likely feature a 1333MHz as well as even larger L2 caches to hide bandwidth issues. While these features may sound expensive, they won't be since the economics of the 45nm process covers these improvements.
I really don't know what to make of an AMD quad core Opteron. AMD has always been very vague on their roadmaps.
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2565
Since the Now column includes their current architecture and the yet to be released sockets M2 and F, the Coming Soon column appears to be what the K10 architecture was suppose to do in 2007. Now it seems the K10 architecture is either canceled or delayed. In any case, we won't see it until 2008.
Now I know that the K10 architecture was designed from the ground up as quad core, does this mean that this is the quad core Opteron AMD is planning to release? Its possible since the earliest estimates I had previously heard for a quad core Opteron was early 2007 which would have been in the K10 timeframe before it was canceled.
However, hearing the vague talk by AMD executives about multicore processors it is quite possible that they also have one based on the K8 architecture. In any case I think Cloverton will beat it to launch. As well, with AMD's 65nm process just starting up and Fab36 still producing 90nm chips, AMD won't likely have volume 65nm chips until the end of 2006. This would mean that a K8 quad core Opteron is more likely at the beginning of 2007. By this time Cloverton's 45nm replacement would already be preparing for launch to give it competition.
On the 4-way server end, things don't really look that bad either. Granted Whitefield was canceled, and with it the integrated memory controller, but Tigerton looks to still free up bandwidth in other ways. Not only will each processor have its own 1333MHz FSB, ie 4 FSBs, but it appears to also incorporate a form of Direct Connect similar to AMD. It seems each processor will also be connected to each other directly so that communication between processors doesn't go through the FSBs. This allows the FSBs to be dedicated to memory traffic. With 800MHz DDR2 to be released with Conroe in H2 2006, its likely that when Tigerton launches in 2007 it will use quad channel 800MHz memory. By 2007 1066MHz DDR2 is also possible. With Intel hinting that Hyperthreading wasn't a total waste and isn't gone for good, its possible that a 2nd generation Merom, Conroe, Woodcrest architecture like Tigerton could have it incorporated. Needless to say I'd like to see a 4 processor quad-core Tigerton system with Hyperthreading. Certainly 32 threads running at the same time would be amazing. I believe that Windows currently allows up to 32 processors so it would work.
http://www.informationweek.com/story/showArticle.jhtml?articleID=172303710&tid=5978
I await angry anti-Intel or anti-me comments.

Hmm, this wink looks more like a squint.