News Zen4 Madness: AMD EPYC Genoa With 96 Cores, 12-Channel DDR5 Memory, and AVX-512

[Admin]

Leaked documents showcase AMD's upcoming EPYC Genoa processors with 96 Zen4 cores, a 12-channel DDR5 memory controller, and Intel's AVX-512 engine for the first time.

Zen4 Madness: AMD EPYC Genoa With 96 Cores, 12-Channel DDR5 Memory, and AVX-512 : Read more

 

[PCWarrior]

TDP: 320W.
Peak power requirement: 700W.

If that was Intel doing this the AMD fbs will be jumping on their power consumption high horse. But now it's AMD it will, of course, all be good and justified.

 

[setx]

If that was Intel doing this the AMD fbs will be jumping on their power consumption high horse. But now it's AMD it will, of course, all be good and justified.

And what is wrong with peak power of 700W? It doesn't affect average power draw in any way, just a requirement for power delivery design.

 

[Samipini]

TDP: 320W.
Peak power requirement: 700W.

If that was Intel doing this the AMD fbs will be jumping on their power consumption high horse. But now it's AMD it will, of course, all be good and justified.

If AMD did this with 28 cores, then we would be outraged too. But this is 96 cores. Your logic amazes me

 

[deesider]

TDP: 320W.
Peak power requirement: 700W.

If that was Intel doing this the AMD fbs will be jumping on their power consumption high horse. But now it's AMD it will, of course, all be good and justified.

700W but for 1 millisecond. If you have a Gigabyte PSU you'll be screwed...

 

[PCWarrior]

If AMD did this with 28 cores, then we would be outraged too. But this is 96 cores. Your logic amazes me

In my post above, I did not take a position of whether any of these power limits are reasonable or not. What I simply stated is that if this news was about Intel cpus, I can guarantee you that the AMD fbs would be posting all over calling them power hungry, fire hazard, spaceheater, nuclear power station, uncoolable, inefficient, etc, etc. But now that’s AMD there are all sorts of justifications: the number of cores, the performance, the duration of power draw, etc, etc. The other day there was an article about Intel’s Alderlake cpus having an increased peak current limit requirement, which is exactly the same thing (peak power requirement is peak current limit requirement for a very brief period (typically 1ms) times 12V ). Just have a look at the comments and read what the AMD fbs were saying. If you want to be amazed look no further to the incredible double standard and hypocrisy of AMD fbs...

 

[Samipini]

In my post above, I did not take a position of whether any of these power limits are reasonable or not. What I simply stated is that if this news was about Intel cpus, I can guarantee you that the AMD fbs would be posting all over calling them power hungry, fire hazard, spaceheater, nuclear power station, uncoolable, inefficient, etc, etc. But now that’s AMD there are all sorts of justifications: the number of cores, the performance, the duration of power draw, etc, etc. The other day there was an article about Intel’s Alderlake cpus having an increased peak current limit requirement, which is exactly the same thing (peak power requirement is peak current limit requirement for a very brief period (typically 1ms) times 12V ). Just have a look at the comments and read what the AMD fbs were saying. If you want to be amazed look no further to the incredible double standard and hypocrisy of AMD fbs...

It's easy why we critique Alder lake when it has only 8 cores and a bunch of garbage cores. it drawing more than 300 watts is just unreasonable for an 8 core. Not counting the small cores cuz it's supposed to be "efficient". We call Intel power hungry because an 8 core uses almost half the power of a 96 core cpu. That just makes no sense. If you still think like before, just remember that usually, more cores = more power consumption, but Intel is same cores, big increase in power consumption.

 

[dalek1234]

Let's do the per core math:
Zen3 EPYC 7763 , 64 cores, has a TDP of 280W. That's 4.375 Watts per core.
Zen4, 96 cores, has a TDP of 320W. That's 3.33 Watts per core.

So Zen 4 has a smaller per-core power draw than Zen3. Looks impressive to me.

 

[PCWarrior]

It's easy why we critique Alder lake when it has only 8 cores and a bunch of garbage cores. it drawing more than 300 watts is just unreasonable for an 8 core. Not counting the small cores cuz it's supposed to be "efficient". We call Intel power hungry because an 8 core uses almost half the power of a 96 core cpu. That just makes no sense. If you still think like before, just remember that usually, more cores = more power consumption, but Intel is same cores, big increase in power consumption.

For Alderlake it’s only the peak power/current requirement that increased (not tdp which remains at 125W neither PL2 which from 250W went down to 228W) and it is exactly that increase in peak power/current requirement, what AMD fbs were bashing Intel for the other day. So when it comes to AMD cpus we should disregard the peak power figure as it only applies for 1ms, yet when it comes to Intel cpus it is justified to used it to bash Intel. That’s exactly the double standard I was talking about.

Also apparently in your understanding, core count is all what matters in declaring something efficient. Apparently, all workloads scale indefinitely and perfectly with cores, and there aren’t any that only benefit from per-core performance increase. So, all these mainstream cpus, including the likes of 5950X, tuned for per core performance must be useless. According to your logic the 5950X is highly inefficient as it is only has 1/8 of the cores yet it has 1/3 the tdp i.e. over 2.5x the power consumption per core compared to these 96-core cpus. By the way, what do you make of the fact that an idle 64-core 3990X system uses 50-60W more power than an idle previous generation Intel/AMD mainstream 8-core cpu system?

Apparently, for you, Skylake performance level of cores are garbage. The same level of per core performance that, by the way, beats (or at worst matches) Zen 2 which is still what AMD is selling with current Threadrippers. So does the 3990W consists of 64 “garbage cores” in your view? I am also sure when AMD makes its own hybrid cpus, you will be consistent and call their little cores “garbage cores” too. You won’t be comparing their performance to that of big cores or find equivalency to big cores from previous architectures.

 

[JayNor]

"Given that such a high number of cores requires massive speeds, a 12-channel controller should be sufficient."

The hpc/ai operations on Intel server chips are memory bandwidth limited. Intel is providing a SPR server chip version for Argonne with 4 stacks of HBM, which effectively adds 32 channels of DDR. I would guess that is sufficient for Argonne, in combination with the Ponte Vecchio GPUs, which have 8 stacks of HBM per GPU (64 DDR channels).

 

[JayNor]

"In addition, it appears that Intel's AVX-512 makes its debut in AMD processors."

does the AMD/Intel cross-license include avx512/dlboost/bfloat16 and other operations?

Intel is adding AMX tiled matrix hardware in SPR for GEMM FMA operations, so we'll see, probably next Monday, what this adds relative to Intel's avx512/dlboost operations.

 

[TJ Hooker]

does the AMD/Intel cross-license include avx512/dlboost/bfloat16 and other operations?

I'm not a lawyer, but I want to say yes based on this:

3.4​

Intel Copyright License to AMD. Subject to the terms of this Agreement, including without limitation Section 5.2(e), Intel grants to AMD, for use in or with an AMD Licensed Product, licenses under Intel’s copyrights in any Processor instruction mnemonic for an instruction developed by Intel, and the related opcodes, instruction operand mnemonics, byte format depictions and short form description (not to exceed 100 words) for those instructions, to copy, have copied, import, prepare derivative works of, perform, display and sell or otherwise distribute such mnemonics, opcodes and descriptions in user manuals and other technical documentation. No other copyright license to AMD is provided by this Agreement other than as set forth in this paragraph, either directly or by implication or estoppel.​

3.5​

AMD Copyright License to Intel. Subject to the terms of this Agreement, including without limitation Section 5.2(e), AMD grants to Intel, for use in or with an Intel Licensed Product, licenses under AMD’s copyrights in any Processor instruction mnemonic for an instruction developed by AMD, and the related opcodes, instruction operand mnemonics, byte format depictions and short form description (not to exceed 100 words) for those instructions, to copy, have copied, import, prepare derivative works of, perform, display and sell or otherwise distribute such mnemonics, opcodes and descriptions in user manuals and other technical documentation. No other copyright license to Intel is provided by this Agreement other than as set forth in this paragraph, either directly or by implication or estoppel.​

 

[JayNor]

Intel added a Data Streaming Accelerator and CXL protocol on SPR, both designed to improve data performance on pcie. It looks like their future plans are to increasingly use pcie ... with their IPU providing access to disaggregated pools of memory and accelerators... GPUs, AI asics, FPGAs, NVM, DDR.

The CPUs might increasingly look like recent GPUs, with more stacks of HBM. I believe there are 8 stacks of HBM2E on Ponte Vecchio, for example.

 

[JayNor]

I'm not a lawyer, but I want to say yes based on this:

3.4​

Intel Copyright License to AMD. Subject to the terms of this Agreement, including without limitation Section 5.2(e), Intel grants to AMD, for use in or with an AMD Licensed Product, licenses under Intel’s copyrights in any Processor instruction mnemonic for an instruction developed by Intel, and the related opcodes, instruction operand mnemonics, byte format depictions and short form description (not to exceed 100 words)​

So, looks like AMD gets to use the mnemonic and encoding, but I don't see guaranteed Intel's hardware implementation... which could be significant with all Intel's additions to handle the throttling for different groups of avx512 instructions.

Some of the leaked pages also indicate issues with interrupts for avx512, which I presume means AMD has their own implementation.

 

[escksu]

TDP: 320W.
Peak power requirement: 700W.

If that was Intel doing this the AMD fbs will be jumping on their power consumption high horse. But now it's AMD it will, of course, all be good and justified.

Not really. Its TDP is 320W because it has 96 cores. TDP per core is jsut 3.33W, this is in fact better than the current 64core 225W Eypc (3.51W per core).

 

[escksu]

Let's do the per core math:
Zen3 EPYC 7763 , 64 cores, has a TDP of 280W. That's 4.375 Watts per core.
Zen4, 96 cores, has a TDP of 320W. That's 3.33 Watts per core.

So Zen 4 has a smaller per-core power draw than Zen3. Looks impressive to me.

Yes, I also did make the same comment. However, having said that, we have to remember TDP is not an accurate representation of power consumption. The reason is that TDP is controlled these days, so the those numbers are set by AMD, not what it actually is.

That is why these cores have very low clockspeed, they run at reduced voltage and core clocks in order to keep within the TDP. If we were to run them at 4GHz on all cores, the power consumption will be easily 800-1000W on full load.

 

[escksu]

"In addition, it appears that Intel's AVX-512 makes its debut in AMD processors."

does the AMD/Intel cross-license include avx512/dlboost/bfloat16 and other operations?

Intel is adding AMX tiled matrix hardware in SPR for GEMM FMA operations, so we'll see, probably next Monday, what this adds relative to Intel's avx512/dlboost operations.

They have this agreement too which does not allow them pursue litigation for any potential patent infringements. So, this means Intel cannot sue AMD for implementing AVX512 in their own CPUs.

https://www.sec.gov/Archives/edgar/data/2488/000119312509236705/dex102.htm

 

[dcbohn2016]

No mention of Samsung's Aquabolt-XL HBM-PIM tech/compatibility?

 

[JayNor]

Intel is adding AMX tiled matrix hardware in SPR for GEMM FMA operations, so we'll see, probably next Monday, what this adds relative to Intel's avx512/dlboost operations.

to answer my own question ... AMX boost is around 8x vs Intel's dlboost 8 bit processing on GEMM operations, based on Intel's slides.

 

[TerryLaze]

Let's do the per core math:
Zen3 EPYC 7763 , 64 cores, has a TDP of 280W. That's 4.375 Watts per core.
Zen4, 96 cores, has a TDP of 320W. That's 3.33 Watts per core.

So Zen 4 has a smaller per-core power draw than Zen3. Looks impressive to me.

So intel was at that point 5 years ago, of having 72 cores run at 260W.
As others already said, without including the clocks, and the performance, just power per core alone is completely useless.
https://ark.intel.com/content/www/u...hi-processor-7290f-16gb-1-50-ghz-72-core.html

It's easy why we critique Alder lake when it has only 8 cores and a bunch of garbage cores. it drawing more than 300 watts is just unreasonable for an 8 core. Not counting the small cores cuz it's supposed to be "efficient". We call Intel power hungry because an 8 core uses almost half the power of a 96 core cpu. That just makes no sense. If you still think like before, just remember that usually, more cores = more power consumption, but Intel is same cores, big increase in power consumption.

If it's anything like rocket lake then 300w is going to be overclocking peak draw while normal usage will be around 125 with 99% performance.
https://www.tomshardware.com/reviews/intel-core-i7-11700k-cpu-review/2