2mb of conroe cache disabled?

[Godiva]

I have read that the cheaper Conroe's, the E6400 and the E6300 have the exact same chip as the more expensive ones, just clocked lower and have 2mb of the 4mb of cache disabled. I bet i'm being an idiot right now but wouldnt it be logical to just keep all 4mb of the l2 cache enabled. Plus i dont see how that could be cheaper considering its the same chip.

 

[xsandman]

I have read that the cheaper Conroe's, the E6400 and the E6300 have the exact same chip as the more expensive ones, just clocked lower and have 2mb of the 4mb of cache disabled. I bet i'm being an idiot right now but wouldnt it be logical to just keep all 4mb of the l2 cache enabled. Plus i dont see how that could be cheaper considering its the same chip.

That is probably correct. That is actually the smart thing to do. This means that any part that is not fast enough to be an E6400 can be sold as an E6300. Also any part that is bad segment in the cache still has the rest of the cache that works, and therefor the bad cache can be disabled and the part can be sold as a 2M version. This is VERY smart when using cache that is so big.

Just think about it.... if Intel didn't do this, all of these parts that are sold as 6300 and below would have to be thrown out. They make more money by selling them as cheaper conroes than throwing them out.

 

[Godiva]

Okay I get it, the chips that have some of the cache malfunctioning, they disable the malfunctioning cache and other parts to make 2 of the 4 mb work, then sell it as a cheaper processor instead of throwing it away as a defective processor.

 

[xsandman]

Okay I get it, the chips that have some of the cache malfunctioning, they disable the malfunctioning cache and other parts to make 2 of the 4 mb work, then sell it as a cheaper processor instead of throwing it away as a defective processor.

Correct. They do the same thing with speed. They also can have a 2M version by design (as jack stated) and this saves die size, which increases yield and volume. This is all based off of binsplit and demand.

Although i dont know if this would be called "redundancy", as i think redundancy is really invincible (sp) to the end user and the same amount of cache is always available. Cache disabling you actually lose the cache.

 

[1Tanker]

I have read that the cheaper Conroe's, the E6400 and the E6300 have the exact same chip as the more expensive ones, just clocked lower and have 2mb of the 4mb of cache disabled. I bet i'm being an idiot right now but wouldnt it be logical to just keep all 4mb of the l2 cache enabled. Plus i dont see how that could be cheaper considering its the same chip.

This is partially correct. The 2 meg version of Conroe is called allendale -- however, during processing if defects cause issue in 2 meg's of the 4 meg L2 cache companies can simply turn off the non-function area of caches, and down brand the product and still seel it. It is called redundancy, and it helps. By doing so you can sell a normally nonfunctional die and still get a return. This is common. There is nothing wrong with the chip, it just will only access 2 of the 4 meg -- this is by design.

The flip side is the die size is large, so both AMD and Intel will also generate a mask set with smaller die targeted with 2 Meg L2 cache and brand those accordingly as well. In such a case, redundancy is still built in (the cache size is more like 2.5 Meg), but the die size is much smaller and you get higher yields and higher thorougput.

JackIt's often been said that Celerons were P4's with the defective cache disabled.

 

[RichPLS]

Okay I get it, the chips that have some of the cache malfunctioning, they disable the malfunctioning cache and other parts to make 2 of the 4mb work, then sell it as a cheaper processor instead of throwing it away as a defective processor.

Precisely --- it is better to sell down than to not sell at all

A fact AMD is learning the hard way lately... but that thought hurts BM so much, it is comforting to envision the mountains of worthless P4's Intel will never be able to sell since they were never wanted anyways!

 

[YO_KID37]

Oh Intel isn't stupid enough to let Pentium 4s just stay there and rust. They Most probably are planning to sell them To the inter-city schools. or they might be desperate enough to give away their stock to the poorest kids in the world. Just like the computers 10X10 or 10X50 or 50X10?? we can find AMD giving away that need cranking and all that jazz., imagine poor kids in africa with crankable Prescotts. LOLLLOLS that's a lotttt of cranking kids!!

 

[RichPLS]

Intel in an act of good will could donate all their older P4's to AMD, and then they could remark them Athlons! to sell as stock... all the while being able to demonstrate a smooth transition front while their design teams finish out the real McCoy on 65nm.

 

[MU_Engineer]

Yes, some lower-cache parts are in fact partially disabled or failed higher-cache parts, but more and more, they are actually separate dies. The Athlon 64 X2 Manchester (512KB) and Toledo (1MB) chips had different codenames as there were two die masks, one for each chips. It turns out that AMD had such good yields on the 1MB products that they didn't have all that many to disable the cache on to sell as 512KB models, so they simply shot 512KB dies to keep up with demand. I imagine that Intel will probably do that with the Core 2 Duo as well as Intel's yields on 65nm are supposed to be very, very good also. It also saves Intel from having to disable larger-die, perfectly functional 4MB chips to meet the demand for 2MB chips when they can use a smaller die 2MB chip from the getgo.

 

[1Tanker]

Yes, some lower-cache parts are in fact partially disabled or failed higher-cache parts, but more and more, they are actually separate dies. The Athlon 64 X2 Manchester (512KB) and Toledo (1MB) chips had different codenames as there were two die masks, one for each chips. It turns out that AMD had such good yields on the 1MB products that they didn't have all that many to disable the cache on to sell as 512KB models, so they simply shot 512KB dies to keep up with demand. I imagine that Intel will probably do that with the Core 2 Duo as well as Intel's yields on 65nm are supposed to be very, very good also. It also saves Intel from having to disable larger-die, perfectly functional 4MB chips to meet the demand for 2MB chips when they can use a smaller die 2MB chip from the getgo.

Ok, but isn't defective cache sort of "the nature of the beast"? Meaning wouldn't Intel/AMD inevitably get a certain amount of chips with defective cache?

 

[MU_Engineer]

Yes, but from what I heard, they don't get all that many defective cache chips to sell, so they need an additional smaller cache die mask and wafer run to make up the difference between demand and supply of disable-able larger-L2 chips.

 

[RichPLS]

8) So would that indicate that Intel is catching up to AMD in yeilds?

 

[MU_Engineer]

Well, I think that you'd have to ask JumpingJack or JKFlipFlop98 about that one, though I bet that Intel's yields are a little better than AMD's. I use the fact that Intel never sold a cache-disabled Pentium D 9xx chip and they could sell them starting at $200 and still be in the black to back that assertion up. The most that Intel could do with a Pentium D 9xx that had bad cache would be to disable an entire core to make it a Cedar Mill P4 with a single 2M cache. I bet they would not do that if only some of the L2 cache is gone, so yields were probably good enough just to toss the few Preslers that had some cache that was defective rather than make an entirely new product line of 2x1MB 65nm Pentium Ds.

 

[The_Abyss]

Yep - many P4s will go overseas. People sometimes forget that there are uses for PCs outside the US.

 

[the_vorlon]

.....

 

[the_vorlon]

Well, I think that you'd have to ask JumpingJack or JKFlipFlop98 about that one, though I bet that Intel's yields are a little better than AMD's. I use the fact that Intel never sold a cache-disabled Pentium D 9xx chip and they could sell them starting at $200 and still be in the black to back that assertion up. The most that Intel could do with a Pentium D 9xx that had bad cache would be to disable an entire core to make it a Cedar Mill P4 with a single 2M cache. I bet they would not do that if only some of the L2 cache is gone, so yields were probably good enough just to toss the few Preslers that had some cache that was defective rather than make an entirely new product line of 2x1MB 65nm Pentium Ds.

Not correct :roll: :roll: :roll: :roll: :roll:

The Pentium D's are not a true dual core, they are, essentially, two single core CPUs joined at the packaging level.

Unlike Core2 and Athlon x2 where the two cores are laid out as adjoining silicon on the original wafer, the two cores on a 8xx and 9xx dual core can and do start out as seperate single cores from different parts of the wafer (or indeed even a different wafer)

A 8xx is basically two 5xx cores on one package

A 9xx is basically two 6xx cores on one package

😛 😛 😛 😛 😛

 

[MU_Engineer]

You are right about both Pentium D chips being MCMs (I thought that Intel had actually put the Pentium D 9xxs on one die, but apparently they did not.) However, the Pentium Ds' cores are a tad different from stock 5xx and 6xx cores:

Pentium D 8xx has two 90nm 1MB L2 cores with EM64T, EIST enabled. This most closely resembles the 5x1 series, but no 5xx chips have EIST. The 6xx ones do.

Pentium D 9xx has two 65nm 2MB L2 cores with EM64T, later steppings have EIST, the 9x0 have VT, the 9x5 ones do not. The PD 9x5 are exactly two Cedar Mill 6x1 cores whereas the PD 9x0 are two 6x2-class chips, although there are only 2 Cedar Mill 6x2 chips- the 3.8 GHz 672 (not seen in a Pentium D) and the 3.6 GHz 662, used in the PD 960. So the rest of the lower-clocked Pentium D 9x0 lineage uses 6x2 class chips not sold individually. Note that the P4 6x0 is a 2MB L2 90nm chip and is not used in a Pentium D.

 

[XiaoYY]

I have read that the cheaper Conroe's, the E6400 and the E6300 have the exact same chip as the more expensive ones, just clocked lower and have 2mb of the 4mb of cache disabled. I bet i'm being an idiot right now but wouldnt it be logical to just keep all 4mb of the l2 cache enabled. Plus i dont see how that could be cheaper considering its the same chip.

According to this link
http://www.techpowerup.com/cpudb/details.php?id=372
The die size of Allendale is 111 mm2, while Conroe has a die size of 143.

 

[mpjesse]

I have read that the cheaper Conroe's, the E6400 and the E6300 have the exact same chip as the more expensive ones, just clocked lower and have 2mb of the 4mb of cache disabled. I bet i'm being an idiot right now but wouldnt it be logical to just keep all 4mb of the l2 cache enabled. Plus i dont see how that could be cheaper considering its the same chip.

This is partially correct. The 2 meg version of Conroe is called allendale -- however, during processing if defects cause issue in 2 meg's of the 4 meg L2 cache companies can simply turn off the non-function area of caches, and down brand the product and still sell it. It is called redundancy, and it helps. By doing so you can sell a normally nonfunctional die and still get a return. This is common. There is nothing wrong with the chip, it just will only access 2 of the 4 meg -- this is by design.

The flip side is the die size is large, so both AMD and Intel will also generate a mask set with smaller die targeted with 2 Meg L2 cache and brand those accordingly as well. In such a case, redundancy is still built in (the cache size is more like 2.5 Meg), but the die size is much smaller and you get higher yields and higher thorougput.

Jack

I make a motion to make you the CPU forum guru.

 

[1Tanker]

The flip side is the die size is large, so both AMD and Intel will also generate a mask set with smaller die targeted with 2 Meg L2 cache and brand those accordingly as well. In such a case, redundancy is still built in (the cache size is more like 2.5 Meg), but the die size is much smaller and you get higher yields and higher thorougput.

Jack

I have to wonder whether the binned(Conroe) parts with defective cache disabled show any difference in, say overclockability vs a specifically manufactured Allendale, or heat output...required voltage...etc. :?

 

[Vein]

I have to wonder whether the binned(Conroe) parts with defective cache disabled show any difference in, say overclockability vs a specifically manufactured Allendale, or heat output...required voltage...etc. :?

I wonder the same thing. In fact, I bet the OEM's from TigerDirect were probably meant to clock higher, and simply are defective 6600-6800's. This would bode well for me 😛. It might just mean that these have more potential than typical CPUs interms of overclocking...

 

[mpjesse]

The flip side is the die size is large, so both AMD and Intel will also generate a mask set with smaller die targeted with 2 Meg L2 cache and brand those accordingly as well. In such a case, redundancy is still built in (the cache size is more like 2.5 Meg), but the die size is much smaller and you get higher yields and higher thorougput.

Jack

I have to wonder whether the binned(Conroe) parts with defective cache disabled show any difference in, say overclockability vs a specifically manufactured Allendale, or heat output...required voltage...etc. :?

Good question. I would surmise that since the extra cache is not being used (electrically), it probably would put out the same amount of heat and use the same amount of voltage.

Unless of course the disabled cache is using electricity.

 

[jimw428]

I have to wonder whether the binned(Conroe) parts with defective cache disabled show any difference in, say overclockability vs a specifically manufactured Allendale, or heat output...required voltage...etc. :?

I wonder the same thing. In fact, I bet the OEM's from TigerDirect were probably meant to clock higher, and simply are defective 6600-6800's. This would bode well for me 😛. It might just mean that these have more potential than typical CPUs interms of overclocking...

Or it could just be wishful thinking. :lol:

 

[jkflipflop98]

The flip side is the die size is large, so both AMD and Intel will also generate a mask set with smaller die targeted with 2 Meg L2 cache and brand those accordingly as well. In such a case, redundancy is still built in (the cache size is more like 2.5 Meg), but the die size is much smaller and you get higher yields and higher thorougput.

Jack

I have to wonder whether the binned(Conroe) parts with defective cache disabled show any difference in, say overclockability vs a specifically manufactured Allendale, or heat output...required voltage...etc. :?

Good question. I would surmise that since the extra cache is not being used (electrically), it probably would put out the same amount of heat and use the same amount of voltage.

Unless of course the disabled cache is using electricity.

When the extra 2 megs is disabled, one of the fuses that is blown is the Vsupply. No power will be drawn by the disabled memory.

 

[JonathanDeane]

The flip side is the die size is large, so both AMD and Intel will also generate a mask set with smaller die targeted with 2 Meg L2 cache and brand those accordingly as well. In such a case, redundancy is still built in (the cache size is more like 2.5 Meg), but the die size is much smaller and you get higher yields and higher thorougput.

Jack

I have to wonder whether the binned(Conroe) parts with defective cache disabled show any difference in, say overclockability vs a specifically manufactured Allendale, or heat output...required voltage...etc. :?

Good question. I would surmise that since the extra cache is not being used (electrically), it probably would put out the same amount of heat and use the same amount of voltage.

Unless of course the disabled cache is using electricity.

When the extra 2 megs is disabled, one of the fuses that is blown is the Vsupply. No power will be drawn by the disabled memory.

Ohhh yeah I thought they laser cut them but I did hear something about cache using a fuse (of sorts lol) good thinking !!!